06-19-2017 01:46 PM
When using an AXI Steam FIFO in AXI4Lite mode, the device tree is generated properly, with a single memory region.
When setting it to AXI4 mode, the device tree is generating the reg entry in the device tree incorrectly.
#address-cells = <0x2>;
#size-cells = <0x2>;
compatible = "simple-bus";
compatible = "xlnx,axi-fifo-mm-s-4.1";
interrupt-parent = <0x4>;
interrupts = <0x0 0x59 0x4>;
reg = <0x0 0xa0000000 0x0 0x10000 0xa0010000 0x10000>;
xlnx,axi-str-rxd-protocol = "XIL_AXI_STREAM_ETH_DATA";
xlnx,axi-str-rxd-tdata-width = <0x20>;
... snip ...
size-cell and address-cell are both set to 2, so there should be two values for each address and size in the reg entry.
First region: 0x0 0xA0000000 0x0 0x10000
Second region: 0xA0010000 0x10000
I believe the line should instead read:
reg = <0x0 0xa0000000 0x0 0x10000 0x0 0xa0010000 0x0 0x10000>;
08-31-2017 10:33 AM