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Visitor jol14
Visitor
598 Views
Registered: ‎01-11-2019

Petalinux 2018.3 build error with concatenated interrupts

Hi all,

I'm experiencing the following build error while using concatenated interrupts in the Vivado block design.

I created a simple block design that can be used to reproduce the error.

The block design contains 20 uart_lite IP's that share one interrupt for every 4 uart's. This will give a total of five interrupts to the Zynq PS.

I did some research and i think this error has something to do with assigning interrupts ID's during the FSBL build. The interrupt numbers are incremented for each uart. Since the PS has only 16 interrupts the assigning fails on interrupt 17.

I would expect that the interrupt ID is only incremented for each set of 4 uart's.

I attached the HDF file to reproduce the problem. I tested this with vivado/petalinux version 2018.2 and 2018.3 and it results in the same error.

 

[INFO] building project
[INFO] generating Kconfig for project
[INFO] oldconfig project
[INFO] sourcing bitbake
[INFO] generating plnxtool conf
[INFO] generating meta-plnx-generated layer
[INFO] generating machine configuration
[INFO] generating bbappends for project . This may take time ! 
[INFO] generating u-boot configuration files
[INFO] generating kernel configuration files
[INFO] generating kconfig for Rootfs
[INFO] oldconfig rootfs
[INFO] generating petalinux-user-image.bb
INFO: bitbake petalinux-user-image
Loading cache: 100% |#########################################################################################################################| Time: 0:00:00
Loaded 3444 entries from dependency cache.
Parsing recipes: 100% |#######################################################################################################################| Time: 0:00:02
Parsing of 2569 .bb files complete (2532 cached, 37 parsed). 3445 targets, 149 skipped, 0 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
Initialising tasks: 100% |####################################################################################################################| Time: 0:00:04
Checking sstate mirror object availability: 100% |############################################################################################| Time: 0:00:10
NOTE: Executing SetScene Tasks
NOTE: Executing RunQueue Tasks
ERROR: fsbl-2018.3+gitAUTOINC+56f3da2afb-r0 do_configure: Function failed: do_configure (log file is located at /home/eal/Documents/test/test/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/temp/log.do_configure.29996)
ERROR: Logfile of failure stored in: /home/eal/Documents/test/test/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/temp/log.do_configure.29996
Log data follows:
| DEBUG: Executing shell function do_configure
| MISC_ARG is  -yamlconf /home/eal/Documents/test/test/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/fsbl.yaml
| APP_ARG is  -app "Zynq FSBL"
| Using xsct from: /opt/pkg/petalinux20183/tools/xsct/SDK/2018.3/bin/xsct
| cmd is: xsct -sdx -nodisp /home/eal/Documents/test/test/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/app.tcl -ws /home/eal/Documents/test/test/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/build -pname fsbl -rp /home/eal/Documents/test/test/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/git -processor ps7_cortexa9_0 -hdf /home/eal/Documents/test/test/build/tmp/deploy/images/plnx-zynq7/Xilinx-plnx-zynq7.hdf -arch 32  -app "Zynq FSBL"  -yamlconf /home/eal/Documents/test/test/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/fsbl.yaml
| INFO: [Hsi 55-1698] elapsed time for repository loading 0 seconds
| Opening the hardware design, this may take few seconds.
| expected integer but got ""
| ERROR: [Hsi 55-1545] Problem running tcl command ::sw_scugic_v3_10::generate : expected integer but got ""
|     while executing
| "format "#define XPAR_FABRIC_%s_%s_INTR %d$uSuffix"  [string toupper $ip_name] [string toupper $port_name] $port_intr_id"
|     ("foreach" body line 86)
|     invoked from within
| "foreach periph $periphs {
| 
|         # get the gic mode information
|         set scugic_mode [common::get_property CONFIG.C_IRQ_F2P_MODE $periph]
| 
|       ..."
|     (procedure "xdefine_gic_params" line 30)
|     invoked from within
| "xdefine_gic_params $drv_handle"
|     (procedure "::sw_scugic_v3_10::generate" line 10)
|     invoked from within
| "::sw_scugic_v3_10::generate ps7_scugic_0"
| ERROR: [Hsi 55-1442] Error(s) while running TCL procedure generate()
| Failed to generate the platform.
| Reason: Failed to generate the bsp sources for domain.fsbl_domain
|     while executing
| "builtin_platform -generate quick"
|     (procedure "platform" line 221)
|     invoked from within
| "platform generate -quick"
|     invoked from within
| "if { $params(ws) ne "" } {
| 	#Local Work Space available
| 	if { $params(pname) ne "" } {
| 		# hwpname/bspname is empty then default it to pname+_hwproj/b..."
|     (file "/home/eal/Documents/test/test/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/app.tcl" line 139)
| WARNING: /home/eal/Documents/test/test/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/temp/run.do_configure.29996:1 exit 1 from 'eval xsct -sdx -nodisp /home/eal/Documents/test/test/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/app.tcl -ws /home/eal/Documents/test/test/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/build -pname fsbl -rp /home/eal/Documents/test/test/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/git -processor ps7_cortexa9_0 -hdf /home/eal/Documents/test/test/build/tmp/deploy/images/plnx-zynq7/Xilinx-plnx-zynq7.hdf -arch 32 ${APP_ARG} ${MISC_ARG}'
| ERROR: Function failed: do_configure (log file is located at /home/eal/Documents/test/test/build/tmp/work/plnx_zynq7-xilinx-linux-gnueabi/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/temp/log.do_configure.29996)
ERROR: Task (/opt/pkg/petalinux20183/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_configure) failed with exit code '1'
NOTE: Tasks Summary: Attempted 2969 tasks of which 2242 didn't need to be rerun and 1 failed.

Summary: 1 task failed:
  /opt/pkg/petalinux20183/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_configure
Summary: There was 1 ERROR message shown, returning a non-zero exit code.
ERROR: Failed to build project
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4 Replies
428 Views
Registered: ‎05-29-2018

Re: Petalinux 2018.3 build error with concatenated interrupts

I experienced the same problem. It fails also when generating a bsp in Xilnx SDK. I put a RTL module instead of the util_reduced_logic IP and the generation worked. But than I had a problem in the device tree generation for the shared interrupt source, to correctly identify the interrupt ID. Hear I had to patch the device_tree/data/common_proc.tcl to add the RTL module in "proc get_intr_cntrl_name".

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Scholar vanmierlo
Scholar
420 Views
Registered: ‎06-10-2008

Re: Petalinux 2018.3 build error with concatenated interrupts

Can you elaborate on "share"? Do you mean you OR 4 interrupt signals together using the Utility Reduced Logic ? And then concatenate the 5 resulting interrupt signals towards the Zynq IRQ_F2P?

Have you tried if it works any better with an AXI Interrupt Controller?

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Visitor jol14
Visitor
415 Views
Registered: ‎01-11-2019

Re: Petalinux 2018.3 build error with concatenated interrupts

I gave up trying to get the shared interrupts working. I placed an additional axi interrupt controller for the uarts. So now they have all unique interrupt ID's and the petalinux project builds. 

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406 Views
Registered: ‎05-29-2018

Re: Petalinux 2018.3 build error with concatenated interrupts

Yes exactly, but instead of using the 'Utility Reduced Logic' from Xilinx just build your own with a RTL module.
You could use an AXI interrupt controller but it will consume some unnecessary resources for this case.
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