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vishu26
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Registered: ‎11-11-2019

Petalinux 2020.2: interrupts information not getting generated in pl.dtsi

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Hi,

I am using Petalinux Version 2020.2. Using Vivado 2020.2, an IP in PL is created. The IP has four PL-PS interrupts an are configured as shown.

pl_ps_interrupts.PNG

The interrupts in the PS are also enabled as shown.

pl_ps_interrupts_enable.PNG

 

Using the above design, I generate .xsa file which I use in the petalinux project.

In the petalinux project, I call

petaliunx-config --get-hw-description

Following this device tree files are generated in <plnx-project> > components > plnx_workspace > device-tree > device-tree

My pl.dtsi file looks like as follows:

pl_dtsi.PNG

The problem is that no interrupt information for PL part is produced by petalinux. So I assume it can be one of the following problems

  1. Etither I need to enable something in Vivado design to activate interrupts in PL.
  2. Or the petalinux is failing to generate interrupt information for the PL part.

I would be glad if someone can help.

Thanks and Regards

Vishav

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stephenm
Xilinx Employee
Xilinx Employee
641 Views
Registered: ‎09-12-2007

The DTG looks for all pins of type interrupt when generating the interrupt node properties. You can go through a concat IP, or a vector logic. The DTG will do a few hops to try find the interrupt source pin.

In your custom IP, this is not the case.

 

So, you have two solutions:

  1. Fix it in HW and regenerate the HW (as discussed above)
  2. Manually add the DT node in your petalinux project (discussed below)

Assuming this is the interrupt here:

int.PNG

This is connected to IRQ_F2P 88

pl_ps.PNG

 

So, you can update the system-user.dtsi with this info (88 - 32 (SPI) = 56)

https://github.com/Xilinx/device-tree-xlnx/blob/master/device_tree/data/common_proc.tcl#L258

 

 

& rt_axi_if_dsbl_netlist_0 {
   interrupt-parent = <&gic>;
   interrupts = <0 56 4>;
};

 

 

 

 

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19 Replies
maps-mpls
Mentor
Mentor
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Registered: ‎06-20-2017

Your pop up windows are highlighting basic interrupt connectivity.  But they mask what is driving those interrupts. 

Is it standard IP from the IP catalog, or custom IP done by you or a hardware designer?

*** Destination: Rapid design and development cycles *** Unappreciated answers get deleted, unappreciative OPs get put on ignored list ***
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hokim
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Registered: ‎10-21-2015

Hi 

Probably the interrupt line of your custom ip is not interrupt type

Did you do step 4 at https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1118-vivado-creating-packaging-custom-ip.pdf#page=42 ?

vishu26
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Registered: ‎11-11-2019

Hi @maps-mpls 

It is a custom IP done by a hardware designer. Can I enable the interrupts on my own or do I need to ask hardware designer?

Thanks & Regards

Vishav

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vishu26
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Registered: ‎11-11-2019

Hi @hokim 

Unfortunately I did not design the custom IP. Is there a way that I can proof if interrupt support is missing in IP block?

Thanks and Regards

Vishav

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hokim
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Scholar
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Registered: ‎10-21-2015

Only interrupt type pin should be connected to IRQF2P

You can check it in vivado pin properties

The interrupt pin should be like this

pin_properties.png

You have to ask hardware designer to set the pin to interrupt type

vishu26
Visitor
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748 Views
Registered: ‎11-11-2019

Hi @hokim 

Thanks for the answer. I am a newbie to Vivado tools. How do I access block pin properties? All I see is block properties.

vishu26_0-1618899782440.png

Thanks and Regards

Vishav

 

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hokim
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Scholar
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Registered: ‎10-21-2015

You have to click not ip but pin of ip

interrupt_pin.png

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vishu26
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742 Views
Registered: ‎11-11-2019

Thanks for help. I found out the pin properties. There is no CONFIG tab in the pin properties and hence no senstivity settings. Can I add them on my own?

vishu26_0-1618900516225.png

 

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maps-mpls
Mentor
Mentor
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Registered: ‎06-20-2017

>It is a custom IP done by a hardware designer. 

If this is a real project, your company is losing money relearning over the course of weeks what could have been taught in training over a few days.

The best way for the hardware guy to solve this quickly is for him to create and package some new IP in a throwaway project, check the interrupt support box, and then look at the generated HDL, and apply the generics and signal names found on that throw away project to his.  Also pay attention to the contents of components.xml.  This is a quick and dirty hackish answer, but it should get you going.  There are better and more elegant ways of doing things, and a lot of unclean hackish ways.  I just highlighted one way.

 

 

*** Destination: Rapid design and development cycles *** Unappreciated answers get deleted, unappreciative OPs get put on ignored list ***
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stephenm
Xilinx Employee
Xilinx Employee
642 Views
Registered: ‎09-12-2007

The DTG looks for all pins of type interrupt when generating the interrupt node properties. You can go through a concat IP, or a vector logic. The DTG will do a few hops to try find the interrupt source pin.

In your custom IP, this is not the case.

 

So, you have two solutions:

  1. Fix it in HW and regenerate the HW (as discussed above)
  2. Manually add the DT node in your petalinux project (discussed below)

Assuming this is the interrupt here:

int.PNG

This is connected to IRQ_F2P 88

pl_ps.PNG

 

So, you can update the system-user.dtsi with this info (88 - 32 (SPI) = 56)

https://github.com/Xilinx/device-tree-xlnx/blob/master/device_tree/data/common_proc.tcl#L258

 

 

& rt_axi_if_dsbl_netlist_0 {
   interrupt-parent = <&gic>;
   interrupts = <0 56 4>;
};

 

 

 

 

View solution in original post

vishu26
Visitor
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628 Views
Registered: ‎11-11-2019

Hi @stephenm 

Thanks for answer. I already tried this. But unfortunately I did not get the expected results. Here is how my sytem-user.dtsi file now looks like

/* default */
/{
chosen {
    bootargs = "console=ttyPS0,115200 earlyprintk uio_pdrv_genirq.of_id=generic-uio";
    };
amba_pl: amba_pl {
                rt_axi_if_dsbl_netlist_0: rt_axi_if_dsbl_netlist@7aa00000 {
                            interrupt-parent = <0x3>;
                            interrupts = <0 29 4>;
                            compatible = "generic-uio";
                        };
                };
};

I successfully compiled the kernel, flashed and booted it on my board. But when I run

cat /proc/interrupts

The result is:

vishu26_0-1619100361031.png

As you can see, there is no interrupt listed for my added custom interrupt. It would be great to know what am I doing wrong here.

Thanks and Regards,

Vishav

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stephenm
Xilinx Employee
Xilinx Employee
623 Views
Registered: ‎09-12-2007

Can you try my DT node that I posted in the previous thread?

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vishu26
Visitor
Visitor
619 Views
Registered: ‎11-11-2019

I get a build error. It does not recognize the label gic. What does it corresponds to? Could that be a problem ? Attached is the build log.

Thanks and Regards

Vishav

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stephenm
Xilinx Employee
Xilinx Employee
596 Views
Registered: ‎09-12-2007

This is the name of the ps interrupt controller. Can you send the XSA?

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maps-mpls
Mentor
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Registered: ‎06-20-2017

>It is a custom IP done by a hardware designer. Can I enable the interrupts on my own or do I need to ask hardware designer?

I'd ask the hardware designer to do what I suggested above, or what @hokim suggested, if it is really custom IP.  (There is more than one way to do it right, and many many ways to do it wrong).

Also, I'd be careful about uploading XSAs to a public forum.  It helps us, as you will see, but you're also sharing more of the design than you might have realized.

Your xlconcat_0 has 8 interrupts in the xsa you posted, not the 4 shown in your first screen capture of xlconcat_0.

And all of them are standard Xilinx IP from the IP catalog, not custom IP.

xilinx.com:ip:axi_quad_spi:3.2
xilinx.com:ip:axi_gpio:2.0
xilinx.com:ip:axi_gpio:2.0
xilinx.com:ip:axi_uart16550:2.0 ; # UART_A
xilinx.com:ip:axi_uart16550:2.0 ; # UART 3
xilinx.com:ip:axi_uart16550:2.0 ; # UART 4
xilinx.com:ip:axi_uart16550:2.0 ; # UART 5
xilinx.com:ip:axi_uart16550:2.0 ; # UART 6

Consequently, the XSA does not seem to match the screen capture you posted, and the fact that these are all commonly used Xilinx IPs means it is not likely the interrupt pins were specified incorrectly.  Did you post the wrong XSA?  Take a screen shot of the wrong .bd?   Misunderstand what your audience would understand by the term "custom IP"?  The only custom IP I see in the block diagram is a module for LEDs, and it doesn't seem to have anything to do with interrupts.

Anyway, good luck, too much chaos from what I am seeing for me to be of help.

*** Destination: Rapid design and development cycles *** Unappreciated answers get deleted, unappreciative OPs get put on ignored list ***
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vishu26
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Registered: ‎11-11-2019

@maps-mpls @stephenm 

I am really sorry for the mistake. I posted the wrong xsa file. Here is the correct one.

Again, please accept my apologies.

Regards

Vishav

 

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stephenm
Xilinx Employee
Xilinx Employee
547 Views
Registered: ‎09-12-2007

So, just to clarify. They better fix is to fix this in HW. However, you can compensate for missing info by manually doing this in the DT.

Can you try update your system-user.dtsi as shown below:

/include/ "system-conf.dtsi"
/ {
};

&rt_axi_if_dsbl_netlist_0 {
interrupt-parent = <&intc>;
interrupts = <0 56 4>;
compatible = "generic-uio";
};

 

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vishu26
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Registered: ‎11-11-2019

Hi @stephenm 

Thanks for the information. This thing worked. However, I have one more question. How do I configure multiple interrupts in the same device? Or do I need to configure a new device for each interrupt?

Regards

Vishav

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stephenm
Xilinx Employee
Xilinx Employee
489 Views
Registered: ‎09-12-2007

Ok, great

You would do this in your driver. Then you handler would determine the source of the interrupt within your IP.

 

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