12-22-2020 01:02 AM
- I got an AXI IP connected to the Xilinx' AXI interconnect.
The IP : data and address buses are 32bits
The Interconnect :data and address buses are 64bits. It has other 64bits devices connected (additionally to the Zynq)
- I've booted a Petalinux on the board (here a zcu104) and tried running a simple C application that reads and writes to the IP registers.
I can read and write perfectly on 64bits aligned addresses of my IP but I can't do the same with 32 bits aligned words.
For example, on the attached picture, I can access 0x0 and 0x8 but I can't access 0x4 : The program crashes. I get
I can't trick it with some mask operation because on a same 64bits block, a 32 bit register could be Write-only and another Read-only.
This is very similar to my issue from here , except that I am also communicating with 64bits devices (without issue).
Attached a simplified diagram of the design and an example memory mapping for the IP I can't communicate with.
12-22-2020 04:43 AM
Are you able to share the logic associated with your 32-b AXI slave design? Xilinx's demonstration designs have a whole slew of bugs within them which might cause such an error, and it'd at least be something worth checking.
01-25-2021 06:53 AM - edited 01-25-2021 06:54 AM
01-25-2021 07:50 AM
That's unfortunate, as that will make it hard to help.
Looks like you might be reduced to trying to debug in hardware--the hardest, most unproductive way to do it. (Sigh).
Have you tried using an AXI Firewall at all? Such a firewall might make it easier to trigger an ILA and see what's actually going on. (It might also mask the bug, so ... there's a tradeoff there.)