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DgN
Visitor
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Registered: ‎09-14-2020

Petalinux - AXI IP connected to AXI interconnect : Can't access unaligned to 64b addresses

Hi,

Context

- I got an AXI IP connected to the Xilinx' AXI interconnect.

The IP : data and address buses are 32bits

The Interconnect :data and address buses are 64bits. It has other 64bits devices connected (additionally to the Zynq)

 

- I've booted a Petalinux on the board (here a zcu104) and tried running a simple C application that reads and writes to the IP registers.

 

The issue

I can read and write perfectly on 64bits aligned addresses of my IP but I can't do the same with 32 bits aligned words.

For example, on the attached picture, I can access 0x0 and 0x8 but I can't access 0x4 : The program crashes. I get

 

Bus error

 

I can't trick it with some mask operation because on a same 64bits block, a 32 bit register could be Write-only and another Read-only.

 

This is very similar to my issue from here , except that I am also communicating with 64bits devices (without issue).

 


Attached a simplified diagram of the design and an  example memory mapping for the IP I can't communicate with.

 

 

diagram.png
mem.png
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4 Replies
dgisselq
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Scholar
465 Views
Registered: ‎05-21-2015

@DgN ,

Are you able to share the logic associated with your 32-b AXI slave design?  Xilinx's demonstration designs have a whole slew of bugs within them which might cause such an error, and it'd at least be something worth checking.

Dan

DgN
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Registered: ‎09-14-2020

@dgisselq ,

Thank you for your answer. Unfortunetly I can't share the logic. Though, the IP perfectly works, even with an Xilinx AXI interconnect with 32bit addresses. 

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dgisselq
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Registered: ‎05-21-2015

@DgN ,

That's unfortunate, as that will make it hard to help.

Looks like you might be reduced to trying to debug in hardware--the hardest, most unproductive way to do it.  (Sigh).

Have you tried using an AXI Firewall at all?  Such a firewall might make it easier to trigger an ILA and see what's actually going on.  (It might also mask the bug, so ... there's a tradeoff there.)

Dan

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DgN
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Registered: ‎09-14-2020

@dgisselq ,

I actually did put an ILA and it looks like there is no request coming out of the Zynq at all.

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