10-23-2020 06:14 PM
Hi there,
I am new to Xilinx and Petalinux environment , so excuse my naive question.
I am using ZCU111 evaluation board and I am trying to use Petalinux.
I understand the build process to get a Petalinux built and executed on board via SD card.
The process as I understand it goes like this:
1- I design in Vivado my system, putting the Zynq MPSoC IP and running the whole process of auto-connecting and verifying , then generating the design and extracting the xsa file using export hardware option.
2- Then I run the petalinux-config --get-hw-description=<my_xsa_file_location>
3- Then I run the petalinux-build command,
4- And then I prepare my SD card by generating the BOOT.BIN, image.ub and boot.scr
Everything up till here I understand.
Now what I don't get is what if I designed a module in the PL that connects, to the MIO pins of the ZYNQ processor? how this is going to map into my petalinux image so to use as a file (open, red/write, direction ...etc).
In other words how the previous process takes care of my I/O or any module I design in the PL using (verilog/VHDL) ..etc
10-23-2020 06:20 PM
Further to my question,
How the petalinux map my inputs/outputs ports/pins on the FPGA, and what names in the gpios does it map to?
I beleive (correct me if I am wrong) that it should go under /sys/class/gpio directory somehow?
How is it mapping it and how can I know which port goes to which naming under the petalinux?