UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
1,121 Views
Registered: ‎05-22-2008

Petalinux driver/module for custom AXI-Lite IP

Jump to solution

 

I am getting my embedded linux system up and running on a ZCU102 board. I used petalinux with the reference BSP and got my linux up and running. I added an echo server application. It works. 

 

I then went back to Vivado, added an custom peripheral for which the CPU interface is an AXI4-Lite Slave. Connected, generated a bit stream, exported the HW.

 

I go back to petalinux, rerun petalinux-config --get-hw-description..

 

Now:

 

in pl.dtsi I see my peripheral...Great

 

in <proj-dir>project-spec/hw-description/drivers/ there is the driver code that Vivado created for my peripheral.

 

I didn't modify the driver at all, so it basically consists of calls to Xil_In32 and Xil_Out32

 

I don't know exactly what I need to do right now. I find my self wanting to just include the header in my application, but when I tried that, compilation of my application failed, because it couldn't find the header. But, even if I could direct it to the header, I feel like that should fail because to talk to hardware I need to make system calls via exposed functions in a kernel module.

 

But if that is the case, then what is the point of the driver that Vivado compiles and Petalinux imports? Do I need to adapt the Driver into a module? I briefly read about using the Userspace IO module, but that seems to not use the Xil_In32 and Xil_Out32 calls.

 

I guess what I'm trying to figure out is, I added a custom peripheral to my hardware, with an AXI4-Lite Slave interface. I then imported said hardware into my petalinux project. What do I need to do now?

Does petalinux automagically create and include the appropriate ko module?

Do I need to create a ko module? from Scratch? or Start with the driver that was imported? or is the driver only really useful for bare-metal use cases?

 

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
1,261 Views
Registered: ‎09-12-2007

Re: Petalinux driver/module for custom AXI-Lite IP

Jump to solution

The tools will create a Baremetal driver that uses the API that you mentioned in the standalone BSP and is not applicable in Linux

If you want to create a driver, I would use the UIO driver as a stating point.

http://www.wiki.xilinx.com/Testing+UIO+with+Interrupt+on+Zynq+Ultrascale

3 Replies
Moderator
Moderator
1,262 Views
Registered: ‎09-12-2007

Re: Petalinux driver/module for custom AXI-Lite IP

Jump to solution

The tools will create a Baremetal driver that uses the API that you mentioned in the standalone BSP and is not applicable in Linux

If you want to create a driver, I would use the UIO driver as a stating point.

http://www.wiki.xilinx.com/Testing+UIO+with+Interrupt+on+Zynq+Ultrascale

Explorer
Explorer
1,078 Views
Registered: ‎05-22-2008

Re: Petalinux driver/module for custom AXI-Lite IP

Jump to solution

thanks stephenm,

 

I have it working with linux seeing my IP as a UIO device, and then I use mmap to get access to the registers. I'm going to have to think about how I want to use this setup, and my first thought is, do any of the AXI IP have prebuilt kernel modules/drivers? 

 

I'm thinking about how my design in the PL will interface to the PS, and I will likely have an AXI Stream Fifo with the PS on one side and custom logic on the other side. 

0 Kudos
Explorer
Explorer
1,063 Views
Registered: ‎05-22-2008

Re: Petalinux driver/module for custom AXI-Lite IP

Jump to solution

So, I've made some headway answering my own question.

 

http://www.wiki.xilinx.com/Linux%20Drivers

 

It looks like what I'm looking for is likely one of the axi_dma drivers.

 

Also,

 

the below post appears to show usage/control of the axi_dma block using mm'ed IO.

 

https://lauri.xn--vsandi-pxa.com/hdl/zynq/xilinx-dma.html