01-10-2020 05:31 AM
I am working with petalinux 2019.1, I have tried to occur my petalinux project. When I followed to below instructions, I can get petalinux project without errors. But my image.ub file is not occurs properly.
source <path to Petalinux/settings.sh>
petalinux-create --force --type project --template zynqMP -s <path to xilinx-zcu104-v2019.1-final.bsp> --name proj1
petalinux-config -c kernel
petalinux-config -c rootfs
petalinux-package --boot --fsbl zynqmp_fsbl.elf --u-boot u-boot.elf --pmufw pmufw.elf --fpga system.bit
01-24-2020 06:08 AM
01-27-2020 11:58 PM
When I copy the boot files to the SD card, and start the Xilinx kit, the system does not boot up. I think my image.ub file size is too small. In my opinion, It should be 120 MB, but it is 18.2 MB.
01-28-2020 12:25 AM
Why do you think your image.ub size should be 120MB? My image.ub files are also around 18MB.
When you say the system does not boot up do you mean that you don't see anything on your serial console window or it hangs after printing some messages? If you see any messages on the console, can you share it?
01-28-2020 10:38 PM
Because, when I create project from BSP (xilinx-zcu104-v2019.1-final.bsp) , image.ub size is 126 MB in pre-built file. But when I create my project from .hdf file, image.ub size is 18 MB. This confused me.
I attached pre-built file
01-29-2020 10:56 PM
When I compared the my project with project which created from BSP, I have realized that my design has not ramdisk image. What could be reason of this?
Also, SD card does not boot in ZCU104, does this result from the ramdisk image?
01-29-2020 11:11 PM
Depending on what you've selected as the root filesystem type in petalinux-config the contents and size of image.ub changes. I think rootfs type for the BSP is INITRAMFS. If you have selected SD card as the rootfs type, root filesystem will not be included in image.ub and the kernel will look for it inside your SD card. You have to extract rootfs.tar.gz file generated by PetaLinux to your SD card's rootfs partition (formatted as EXT4) so you can boot into your OS.
01-30-2020 03:48 AM
If you share the boot log I'll try to help. If you don't see anything on the serial terminal then there might be a connection/driver issue or the board is not in the correct boot mode (JTAG, SD, etc.). Please make sure you are listening to the correct serial COM port.
01-30-2020 06:11 AM
When I work with images (created from BDP) in pre-built file, there is a no problem. But after building my petalinux project (from a hdf file which I generated through Vivado), I copy the BOOT.bin and image.ub from petalinux-project/images/linux to the SD card. When I try to start the FPGA, setting it to sd boot mode the console stays empty and the LEDs are red as well. I want the FPGA to boot up properly with the image files from my project.
02-16-2020 10:29 AM
I'm using Vivado/Petalinux 2018.2.
When I try to migrate my ZC702 FPGA design to TE0745 board, I lived same problem with you.
To solve this issue, I started from scratch. I used base Trenz FPGA design to prove UART communication. Because in FPGA ZYNQ7 timing settings are completely different.
After that I ported my FPGA design to new one, so thus ZYNQ7 settings were correct and I can run my own design without any problem.
02-17-2020 11:30 AM
what do you see when you boot? Can you share the boot log?
Also, if you are using a zcu104 board, and want to have custom HW design then you should use the flow below:
petalinux-create -t project -s <path to bsp>.bsp
cd <plnx proj>
petalinux-config --get-hw-description=<path to hdf>
rm -rf component
petalinux-build -x mrproper
petalinux-package --boot --fpga system.bit --u-boot
This flow should have all the BSP settings, devicetree. However, will use your custom hw design.
If this doesnt boot, then you need to share the bootlog or else we cant see what the issue is
02-18-2020 06:00 AM
I followed instructions you said, but it didn't work. I couldn't see anything in bootlog.
02-18-2020 06:15 AM
As my understanding from your words:
Your putty window says: yo do not have UART communucation.
When you boot your device, if status leds are red, it means you can not locate your fpga into your chip also.
I think, your first problem is not petalinux, instead booting your device with your BOOT.BIN and image.ub files.
To be sure, your files are properly created, please try to delete old files (BOOT.BIN and image.ub) and regenarate them.
You said, I tried with prebuild images and it worked. this means your sd card partitons is ok and your board conf. is also ok.
Whenever your FPGA status leds turns to green and if you have again nothing on your console, then you need to try different ports.
02-18-2020 07:10 AM
I deleted old files and I started everything from the beginning but it didn't work. May it causes from my Vivado Design?
Because, I created hardware design for zcu106 from .tcl file. I followed the instructions in this URL (https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/115933296/Zynq+UltraScale+MPSoC+VCU+TRD+2019.1+-+Run+and+Build+Flow)
After that, I adjusted the design according to zcu104, and exported hdf file.
But I am not sure, ıs the problem originating from here.
02-18-2020 12:36 PM
Have you tried "petalinux-boot --jtag" https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug1144-petalinux-tools-reference-guide.pdf page 45? Also I think that you should check your "petalinux-config" to see "image packaging" and boot options (I don't remember how was it named there, but there are options about BOOT.BIN location, image.ub and all the others).
From my own exprience you should build minimal petalinux package to see if it is working, try jtag boot option that I mentioned before. If that works then it means that you have formated sd-card wrong or have wrong files inculded in BOOT.bin or sd-card partition.
02-18-2020 12:53 PM
I think the issue is you are porting from one board to another.
Did you update the pcw set t io ngs as the ddr settings would be different.
You should start in vivado, create a project targeting your board, add tyhe zynq PS and use the preset values, and go from there.
02-19-2020 02:06 AM
I m agree with @stephenm , this advice is what I mentioned my previous post.
First you need generate a base design for your board. Then you need to port other IP cores, logics to yours.
You need to make initial ZYNQ settings properly, the easiest way is starting new project and selecting your board and add new ZYNQ IP core, it comes with its own settings.
Or you can use your current ported design. Delete ZYNQ Ip core, change target board to yours, add new ZYNQ IP core, it is added with preset values.