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Visitor
Visitor
1,460 Views
Registered: ‎10-11-2018

Problem addressing AXI BRAM from linux

Hello,

In my project (with a Zedboard), data is read written to a BRAM from a custom IP, and then I use an AXI BRAM controller to interface it and make it accessible to the Petalinux (2018.2) running on the ARM.

Fig 1: Memory and controllerFig 1: Memory and controllerThe base address for the controller is 0x4200_0000 with a range of 8K (up to 0x4200_1FFF). The memory has 8K positions too, each with a width of 32 bits.

To ensure the problem isn't on the custom IP, the memory is initialized with a .coe file simply numbering each of the 8K address (so address 1 contains 0x01, etc, up to 0x1fff).

The problem comes when attempting to read those values from Linux. Using devmem 0x42000001 on command line returns 0x04000000 and the following:

Alignment trap: devmem (1257) PC=0x0001ca94 Instr=0xe7902005 Address=0xb6f9d2fd FSR 0x011

Which seems to indicate Linux is expecting each address value to map to a byte, not a 32bits word. The alignment traps happen until devmem 0x42000004, which returns 0x00000004, the correct value for the fourth direction, but the values in addresses not multiple of 4 can't be accessed. devmem 0x42000002 returns 0x00040000 (notice the 0x04 shifting) as well as the alignment trap. I've found the same problem with my original python script which uses mmap to map /dev/mem: I have to read each 4 address values since each individual address seems to map to a byte, but that means I only get one of each four values.

Has anyone found a similar problem? Am I using a wrong configuration?

Thank you for your help

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Moderator
Moderator
1,436 Views
Registered: ‎12-04-2016

Re: Problem addressing AXI BRAM from linux

Hi @nfranch

 

If you see this wiki, 

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842412/Accessing+BRAM+In+Linux

You need to take care of these details, while accessing memory

  • The /dev/mem driver requires root privileges which may not be desired in all systems.
  • The O_SYNC flag in the open() of the /dev/mem driver would not be required in a cache coherent system as described at Cache Coherency.
  • Normal memory can be accessed unaligned without issues while device/strongly ordered will cause exceptions.
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Visitor
Visitor
1,419 Views
Registered: ‎10-11-2018

Re: Problem addressing AXI BRAM from linux

Hi @shabbirk

Thanks, I indeed had already seen the wiki page you linked.

Using root access is not a problem in this application, and the O_SYNC flag is not even an issue since I'm only trying to read, not write to the memory.

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Visitor
Visitor
1,362 Views
Registered: ‎10-11-2018

Re: Problem addressing AXI BRAM from linux

To add more information to the question, I made the next drawing (because it was not easy to explain to fellow workers):

Memory adressing problemMemory adressing problem

 What it shows is that the memory is only showing the data in the addresses multiple of 4. I never see any part of the data between the multiple of 4 addresses.

I'm not sure if this isn't a bug with the AXI BRAM Controller IP, which to my understanding is in charge of translating the Linux addressing to the appropriate memory addressing.

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Observer
Observer
733 Views
Registered: ‎01-26-2009

Re: Problem addressing AXI BRAM from linux

I just spent an hour teaching a grad student about this. The problem is that the designers of the AXI BRAM Controller made a mistake by having it emit A0 and A1. Those address bits specify which byte in a 32-bit word are to be accessed, when a byte access is being performed.

The address bits of your 32-bit wide BRAM memory need to be connected to A2 and up on the AXI bus.

It would be great if the AXI BRAM controller actually had a BRAM address bus that matched the BRAM, but alas.

 

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Moderator
Moderator
708 Views
Registered: ‎09-12-2007

Re: Problem addressing AXI BRAM from linux

Yes, this is expected. You need to be on a 32 bit boundary.

 

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Observer
Observer
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Registered: ‎08-08-2018

Re: Problem addressing AXI BRAM from linux

I had same problem:

2 port BRAM with 32b data width. It is written by PL and read by PS. But PS has 4Byte address alignment.

I solved it like @nixiebunny wrote: remove A0 and A1. I used a "Slice" IP for that:

 

20191016_PS_BRAM_Access.PNG

That works for me.

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