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Registered: ‎10-29-2018

Problem building FPGA manager with 2018.3 release


I am currently going through this article

Solution ZynqMP PL Programming 

We are using a Ultrascale MpSoc and Yocto release 2018.3 from Xilinx.

I am trying to include fpga-manager-script and fpga-manager-util in the image but the build fails with the error message "base dtbo was not generated. Check logs, make sure overlays are enabled".

After looking at the recipe I thought, it is not working because in our kernel source we rename the pl.dtsi and pcw.dtsi files to use a prefix. However, even changing that did not help. I double checked that all the CONFIG options as required are enabled. Just to be doubly sure, I also invoked menuconfig from within Yocto using bitbake, force recompiling the kernel and then trying to build fpga-manager. However, the same error message persists.

Can someone tell me what else I might look at or might be missing?

Is it necessary for some kind of overlay entry to be present in the device tree for this to work? Currently, we do not have any. The end goal is to be able to flash a FPGA firmware/bitstream at runtime.



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Registered: ‎10-04-2017

I had a problem with this also and it was because this enable overlays in the device tree and this breaks the build.   There is a patch that I found here on the forums to one of the tcl scripts that fixed the problem.   Sorry, I don't have that reference right now.

  However. if you just want to use the utility to load bitstream, you can add fpga-util to the rootfs instead of enabling fpga manager in the config and everything builds fine.


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