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Participant
Participant
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Registered: ‎04-27-2018

QSPI GENFIFO POLL bit not work

Hi all,

I am using zcu102 to access QSPI flash. Flash write and read is OK.
Now i am trying to use GENFIFO register's poll function to poll the
completion status of flash erase/program ,whcih is written in [ug1085 chapter 24 (page 648)] datasheet .

I have gone through the datasheet and these were the steps i have used.

1.config poll register:enable both upper and lower bus mask,set mask with 0x7F,and set poll data with 0x80
        (i am trying to poll flash's flag register status,value 0x80 (bit 7) indicate erase/program operation succeed.
         also i am using two flash chip working in Dual SS paralle mode)
2.make a receive genfifo command with poll bit ON to read flag status.
3.when RXFIFO NOT EMPTY interrupt comes, read RXFIFO

The problem is i can not always read back 0x80 from RXFIFO,
sometime it is 0x00,which means in erase/program processing.  

Refer to the datasheet:
"The poll bit of the generic FIFO is used to continuously read the status of SPI device until it
matches with the value in the POLL_DATA field of the poll register. The data read from the
SPI device is written into the RXFIFO."
Does it mean i can not read anything from RXFIFO until it "matched"?
If that's true,my configuration seems not work.

Can anyone please tell me what else should be done to use GENFIFO's poll function?

thanks.

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