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Visitor
Visitor
4,638 Views
Registered: ‎06-27-2013

QSPI access causes mmc to stop working

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Our custom board has an eMMC attached to sd0 and Dual Stacked 16MB NOR devices attached to the QSPI. Under Linux (3.10 from the 14.7 release) I can successfully simultaneously access filesystems on both the eMMC and the 1st NOR device. Any access to the 2nd QSPI NOR (flash_eraseall or mount of a previously formatted flash) and then a subsequent access to the eMMC results in:

 

mmc0: Timeout waiting for hardware interrupt.

 

Examining /proc/interrupts there are indeed no further interrupts from SD0 and use of debugfs shows the sdhci interrupt doesn't occur even though the enables look correct.

 

Anyone have any pointers as to how to investigate further ?

 

 

 

 

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Visitor
Visitor
6,013 Views
Registered: ‎02-27-2013

I have a similar issue when using NAND (see post Zynq-NAND-SDIO-Conflic http://forums.xilinx.com/t5/Embedded-Processor-System-Design/Zynq-NAND-SDIO-Conflict/m-p/363263#M9714).

I suspect you do not have a card detect set for your eMMC. (Although why would anyone expect it to be necessary?) QSPI1.CS1 happens to be MIO0, which in turn happens to be the default CD (and WP) lines for SDIO0 and SDIO1.  There is no 'disable' setting in the register, but you can change the pin.  Look for registers SD0_WP_CD_SEL/SD1_WP_CD_SEL [Addresses 0xF80008300x/F8000834]. Switching bit 18 in 'Host_control_Power_control_Block_Gap_Control_Wakeup_control' [also 0xE0100028] did not seem to affect the operation.


I ended up generating a bitfile for boot because the EMIO value appears to be unstable unless the logic is programmed.

 

 

If you are using Vivado, can you confirm if these registers are being set correctly?  In ISE 14.6 and 14.7, the EMIO setting would not set the registers in the FSBL and I had to hand edit the ps7_init.c file.  To my knowledge Xilinx has not issued a fix.

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Xilinx Employee
Xilinx Employee
4,630 Views
Registered: ‎08-01-2012

Please check whether below Answer records could help in addressing the issue

 

(Xilinx Answer 50250)

 

 

 

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

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Visitor
Visitor
6,014 Views
Registered: ‎02-27-2013

I have a similar issue when using NAND (see post Zynq-NAND-SDIO-Conflic http://forums.xilinx.com/t5/Embedded-Processor-System-Design/Zynq-NAND-SDIO-Conflict/m-p/363263#M9714).

I suspect you do not have a card detect set for your eMMC. (Although why would anyone expect it to be necessary?) QSPI1.CS1 happens to be MIO0, which in turn happens to be the default CD (and WP) lines for SDIO0 and SDIO1.  There is no 'disable' setting in the register, but you can change the pin.  Look for registers SD0_WP_CD_SEL/SD1_WP_CD_SEL [Addresses 0xF80008300x/F8000834]. Switching bit 18 in 'Host_control_Power_control_Block_Gap_Control_Wakeup_control' [also 0xE0100028] did not seem to affect the operation.


I ended up generating a bitfile for boot because the EMIO value appears to be unstable unless the logic is programmed.

 

 

If you are using Vivado, can you confirm if these registers are being set correctly?  In ISE 14.6 and 14.7, the EMIO setting would not set the registers in the FSBL and I had to hand edit the ps7_init.c file.  To my knowledge Xilinx has not issued a fix.

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Visitor
Visitor
4,612 Views
Registered: ‎06-27-2013

Thanks for the pointer on the CS, this was the issue. I had broken-cd set in device-tree which I assumed would be sufficient. Luckily we have just rev'ed our board and as a nicety I had asked for CD/WP to be pulled up/down as appropriate for our eMMC.

 

Mapped the pins correctly and the issue has been resolved. Bit of a shame that hsving CD/WP disabled as we previously had doesn't do the "right thing".

 

Thanks again

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3,616 Views
Registered: ‎07-15-2014

Hi,

 

Thanks for this information, I had a similar issue with SD card driver emitting timeout messages when starting to use QSPI in Linux. I have found another workaround though, I am posting it here in case it is of interest for anyone: the SDHDCI controller can use an internal test signal as carrier detect instead of the pin state. This is controlled by using bits 6 and 7 in the SDHCI host control register (offset 28h).

 

Regards.

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