05-31-2015 05:23 PM
I have a Zynq 7000 Development board. I have been using Xilinux as the Linux distribution, using a Xillybus demo bundle to just play around with the distribution without doing anything application wise. Recently however I have been using Vivado 2014.4 to create a custom logic design using the Programmable Logic (PL).
My question is: I have successfully generated a bitstream (.bit file) from my Vivado design and would like to continue using Xilinux as the Linux distribution. Since I implemented custom logic and added some peripherals, do I need to also generate a new BOOT.bin and device tree so that Xilinux will recognize the changes in the hardware? Or does the new bitstream handle all of that? Will Xilinux know about the new peripherals I added in my design from the bitstream file alone or do I need to update the device tree and/or BOOT.bin file?
I am new to FPGA so I'm sorry if this is a dumb question. Any help would be very much appreciated.
05-31-2015 08:52 PM
If you are just planning on accessing your peripheral via memory map (search for mmap for more info), then all you should need to do is update the BOOT.bin file with the new bit file and also update the device tree (.dts) file with an additional extra for your peripheral. This assumes your device is a simple AXI peripheral. If it is in the FPGA fabric and needs no custom interface, then the device tree doesn't need updating. If you touch the DTS file, then remember to recompile and update the .dtb output file.
06-01-2015 03:14 AM
06-01-2015 04:34 PM
Thank you both for the replies. I have the udpated .bit, I updated the FSBL.elf, and am now working on compiling the .dts into .dtb but am having issues there. I have a virtual machine running Ubuntu.
Whenever I try to run the following command to compile the .dts, I get:
chris@Chris-VirtualBox:~/device_tree_bsp_0$ dtc -I dts -O dtb -o system.dtb system.dts
Error: pl.dtsi:76.22-23 syntax error
FATAL ERROR: Unable to parse input tree
It's driving me nuts. I've been trying for hours to compile the .dts and everything I've found online as suggestions to solve the issue are not working. Any ideas?
06-02-2015 01:06 PM - edited 06-02-2015 01:07 PM
sorry but the previous answer is wrong.
you need to modify the bootloader when you modify the Zynq properties in Vivado:
ex. modifying FPGA_CLKs in the Zynq IP - Clock management tab.
because the CPU is responsible for the FPGA initialization, any modification won't be applied if it's different from the previous initialization.
You need to update the devicetree if you write/modify/want to use a module which is probed by the system at runtime:
ex. design an FPGA application using the AXI-DMA IP, add the 'axi-dma' node to the devicetree, take advantage of xilinx's driver supporting DMA for this guy in the Linux kernel.
Therefore, you can use any other hardware apps. without modifying nor rebooting your linux system:
cat my_bistream > /dev/xdevcfg -- flash the FPGA using the Xilinx driver (linux-xlnx kernel)
if you need to access your custom peripheral with a memory map, that's where we usually use the devicetree to retrieve the base_address information, but you can also get started quickly using the /dev/mem module.
06-02-2015 01:15 PM
Thank you for clearing that up. I don't think I changed any of the ZYNQ properties such as the CLK as you suggested. I did however add a UART0 (by default only UART1 is enabled, so I went into Vivado, clicked Customize IP on the processing system block and enabled UART0). In that case, is a new bootloader required for the UART0?
I know for sure that I need a new device tree because I intend to use the VDMA IP and want to use the Xilinx VDMA driver to use it. But that is the issue I am currently having, I cant' compile the .DTS file from the SDK into a .DTB. I keep getting the error I mentioned in my previous post: "Fatal Error: Unable to parse input tree" Any suggestions there?