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Adventurer
Adventurer
4,545 Views
Registered: ‎03-19-2008

Reboot problem when QSPI is in quad I/O mode

Dear Xilinx community.

I'm glad the linux drivers are now supporting the quad mode I/O spi in order to access more than 16 mb of memory (limit of the legacy 3-byte spi addressing mode).

The difference can be seen during the boot process:

 

-- old version from petalinux v2013.04 --

xqspips e000d000.ps7-qspi: master is unqueued, this is deprecated
m25p80 spi1.0: found s25fl256s1, expected m25p80
m25p80 spi1.0: fallback to 3-byte address mode <=
m25p80 spi1.0: maximum accessible size is 16MB <=
m25p80 spi1.0: s25fl256s1 (32768 Kbytes)

 

-- new version from git --
xqspips e000d000.ps7-qspi: master is unqueued, this is deprecated
m25p80 spi1.0: found s25fl256s1, expected m25p80
m25p80 spi1.0: s25fl256s1 (32768 Kbytes)

The problem is that with the new version from git I cannot succesfully reboot anymore.

If I issue the reboot command the ps hangs and If i configure the wdt to trigger a ps reset It seems that everything resets (also the pl), but the ps does not boot anymore.

 

I am using a Spansion S25FL256 qspi flash and it is stated that even when configured in quad i/o mode (register SR1[1]=1) it should correctly handle legacy serial requests.

 

Has anybody else noticed this behaviour?

Thanks.

Giulio

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Adventurer
Adventurer
4,461 Views
Registered: ‎03-19-2008

It seems in fact to be related to answer record #57744

http://www.xilinx.com/support/answers/57744.html

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Adventurer
Adventurer
4,343 Views
Registered: ‎03-19-2008

I designed the new board with the watchdog reset going into the vhdl and then coming out to reset the qspi flash.

Reset line can be held low for a customizable amount of time and after that it reboots the cpu aswell.

This solution would be able to automatically reset cpu in case of disaster and watchdog timer expiration may easily be forced by code.

 

I just would like to know if may I assume that FPGA pins are high impedance before FPGA configuration (e.g. after cpu boot but before FPGA bitstream is fetched from flash and thus loaded to FPGA).

I tested on a few pins and it seems so, but could not find any mention to it in the UG585 Zynq reference manual nor UG470 Spartan 7 Configuration user guide.

 

May somebody confirm?

Many thanks and best regards.

Giulio

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