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Registered: ‎06-07-2018

Reduce RAM access bus width for U-Boot and Xilinx


Before my question confuses you, let me clarify that I am using PicoZed 7030 evaluation board with FMC carrier board v2 and that I have already reduced the Bus width from 32-bit to 16-bit in Vivado.

This has also resulted in reduction of usable RAM from 1 GB to 512 MB.

Now what I want to try is the following:

1. Instead of using the 16-bit bus width, I want to make sure that either the U-Boot or the kernel or both use a 8-bit bus width instead of the full 16-bit bus width. How can this be done?

2. Will this also reduce the available memory space from 512 MB to 256 MB?

3. Is it possible to use an 8-bit bus width on a 512 MB or 1 GB memory space? i.e 16/32-bit address width and 8-bit data access width?

The idea is to benchmark RAM performance. Please help ! I thank you in advance for any help provided by you.


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