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Observer
Observer
7,043 Views
Registered: ‎03-23-2015

Reference HDL design for Zynq Releases

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Hi,

 

I'd like to work off of the reference design provided by the Xilinx wiki. Where can I find the Vivado HDL design that was used to create the pre-built Zynq Releases:

 

http://www.wiki.xilinx.com/Zynq+Releases

 

 

Thanks!

 

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Xilinx Employee
Xilinx Employee
13,054 Views
Registered: ‎03-13-2012

It's pretty much the templates in Vivado. You may have to do some adjustments depending on your platform. but for the Zed this is it:

set project_name "zed"
set part xc7z020clg484-1

set version "2015.1"
set board [get_board_parts -latest_file_version -filter [list BOARD_NAME==$project_name]]
set project_dir vivado/$project_name

create_project $project_name $project_dir -part $part
set_property board_part $board [current_project]

create_bd_design "design_1"
create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7 processing_system7_0
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" }  [get_bd_cells processing_system7_0]
set_property -dict [list CONFIG.PCW_USE_M_AXI_GP0 {0} CONFIG.PCW_EN_CLK0_PORT {0} CONFIG.PCW_EN_RST0_PORT {0}] [get_bd_cells processing_system7_0]

make_wrapper -files [get_files $project_dir/$project_name.srcs/sources_1/bd/design_1/design_1.bd] -top
add_files -norecurse $project_dir/$project_name.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v

update_compile_order -fileset sources_1
update_compile_order -fileset sim_1

generate_target all [get_files  $project_dir/$project_name.srcs/sources_1/bd/design_1/design_1.bd]

file mkdir $project_dir/$project_name.sdk
write_hwdef  -file $project_dir/$project_name.sdk/design_1_wrapper.hdf

close_project
exit

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Xilinx Employee
Xilinx Employee
13,055 Views
Registered: ‎03-13-2012

It's pretty much the templates in Vivado. You may have to do some adjustments depending on your platform. but for the Zed this is it:

set project_name "zed"
set part xc7z020clg484-1

set version "2015.1"
set board [get_board_parts -latest_file_version -filter [list BOARD_NAME==$project_name]]
set project_dir vivado/$project_name

create_project $project_name $project_dir -part $part
set_property board_part $board [current_project]

create_bd_design "design_1"
create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7 processing_system7_0
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" }  [get_bd_cells processing_system7_0]
set_property -dict [list CONFIG.PCW_USE_M_AXI_GP0 {0} CONFIG.PCW_EN_CLK0_PORT {0} CONFIG.PCW_EN_RST0_PORT {0}] [get_bd_cells processing_system7_0]

make_wrapper -files [get_files $project_dir/$project_name.srcs/sources_1/bd/design_1/design_1.bd] -top
add_files -norecurse $project_dir/$project_name.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v

update_compile_order -fileset sources_1
update_compile_order -fileset sim_1

generate_target all [get_files  $project_dir/$project_name.srcs/sources_1/bd/design_1/design_1.bd]

file mkdir $project_dir/$project_name.sdk
write_hwdef  -file $project_dir/$project_name.sdk/design_1_wrapper.hdf

close_project
exit

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Observer
Observer
7,018 Views
Registered: ‎03-23-2015

Thanks!

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