11-19-2012 09:43 AM
Hello,
I am confused what is the right interrupt number for a custom logic interrupt.
The MHS file looks:
BEGIN processing_system7
PARAMETER INSTANCE = processing_system7_0
PARAMETER HW_VER = 4.02.a
.
.
PORT IRQ_F2P = chipscope_trigger_0_Trigger
.
.
END
According to ds871_processing_system7.pdf this should be interrupt 61.
So the dts file looks:
observer@44000000 {
compatible = "nT,observer-1.01.a";
reg = < 0x44000000 0x10000 >;
interrupts = <0 61 4>;
interrupt-parent = <&gic>;
} ;
The driver picks up the interrupt number as in the dts:
~ # cat /proc/interrupts
CPU0 CPU1
29: 25626 28831 GIC twd
40: 1005 0 GIC xdevcfg
43: 11 0 GIC xttcpss clockevent
45: 0 0 GIC pl330
46: 0 0 GIC pl330
47: 0 0 GIC pl330
48: 0 0 GIC pl330
49: 0 0 GIC pl330
54: 13559 0 GIC eth0
56: 37 0 GIC mmc0
61: 0 0 GIC observer
72: 0 0 GIC pl330
73: 0 0 GIC pl330
74: 0 0 GIC pl330
75: 0 0 GIC pl330
82: 169 0 GIC xuartps
IPI0: 0 0 Timer broadcast interrupts
IPI1: 973 1203 Rescheduling interrupts
IPI2: 0 0 Function call interrupts
IPI3: 67 6 Single function call interrupts
IPI4: 0 0 CPU stop interrupts
Err: 0
However the Interrupt handler is never thrown (hw was verified with chipscope).
There are several threads in this forum saying IRQ_F2P[0] is IRQ_F2P[15], IRQ_F2P[1] -> IRQ_F2P[14] and so on.
Another one says 32 has to be substracted.
So maybe someone can clarify the relation between the mhs file and the dts file.
Has the interrupt handling changed between kernel versions?
Thanks,
Marco
11-28-2012 08:16 AM
Hello John,
this works for me:
observer@44000000 {
compatible = "nT,observer-1.01.a";
reg = < 0x44000000 0x10000 >;
interrupts = <0 59 1>;
interrupt-parent = <&gic>;
} ;
Kernel maps it to #91:
~ # cat /proc/interrupts
CPU0 CPU1
29: 22299 25128 GIC twd
40: 989 0 GIC xdevcfg
43: 11 0 GIC xttcpss clockevent
45: 0 0 GIC pl330
46: 0 0 GIC pl330
47: 0 0 GIC pl330
48: 0 0 GIC pl330
49: 0 0 GIC pl330
54: 5070 0 GIC eth0
56: 879 0 GIC mmc0
72: 0 0 GIC pl330
73: 0 0 GIC pl330
74: 0 0 GIC pl330
75: 0 0 GIC pl330
82: 1382 0 GIC xuartps
91: 107 0 GIC observer
Only one signal is connected to PORT IRQ_F2P
The core generates only a pulse so the interrupt is configured for edge.
The kernel device tree parser adds #32
I find this quite strange and not well documented. However, I hope this helps people having the same problem.
Thanks and regards,
Marco
11-19-2012 01:12 PM
The definitive answer is to look at the source for the PS wrapper at <install>\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v4_02_a\hdl\verilog\processing_system7.v
Search for 'irq_f2p'. Padding occurs on the least significant portion of the 20bit irq bus into the PS. Or, to get a 1 to 1 representation, configure the irq portion of the zynq tab as 16 interrupts.
11-22-2012 04:42 AM
Hello John,
can you not confirm as a Xilinx ZYNQ specialist that "PORT IRQ_F2P = chipscope_trigger_0_Trigger"
will mean that I have to have
interrupts = <0 61 4>;
interrupt-parent = <&gic>;
in the dts file?
So I know that the cause is somwhere else.
Thanks,
Marco
11-22-2012 03:21 PM
You still have to consider the irq remapping that's done in hardware. The PORT IRQ_F2P is a bus that's defined as (C_NUM_F2P_INTR_INPUTS-1) downto 0. If C_NUM_F2P_INTR_INPUTS=1, then you have port IRQ_F2P(0 downto 0)=chipscope_trigger.
Now, within the processing_system7 wrapper, since C_NUM_F2P_INTR_INPUTS is not 0 and is not 16, you will have the assignment:
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ, IRQ_F2P[(1-1):0], irq_f2p_null[(15-1):0]};
(Sorry, I'm mixing vhdl and verilog)
So in the end, the actual signals on the PS for irq_f2p are:
irq_f2p[19:0] = Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ, chipscope_trigger, 15'b0
So, with C_NUM_F2P_INTR_INPUTS=1, chipscope_trigger is actually on bit 15 of irq_f2p at the PS.
So SPI: Number 91.
Without testing, and using google, I would say:
interrupts = <0 75 4>
Google shows that 0=SPI, so the second number is the IRQ ID# of 91-16. If the first value was non-zero (private irq), then the calculated value would have been the IRQ ID# minus 32.
With the type=4, make sure the chipscope trigger is set as level high.
11-28-2012 08:16 AM
Hello John,
this works for me:
observer@44000000 {
compatible = "nT,observer-1.01.a";
reg = < 0x44000000 0x10000 >;
interrupts = <0 59 1>;
interrupt-parent = <&gic>;
} ;
Kernel maps it to #91:
~ # cat /proc/interrupts
CPU0 CPU1
29: 22299 25128 GIC twd
40: 989 0 GIC xdevcfg
43: 11 0 GIC xttcpss clockevent
45: 0 0 GIC pl330
46: 0 0 GIC pl330
47: 0 0 GIC pl330
48: 0 0 GIC pl330
49: 0 0 GIC pl330
54: 5070 0 GIC eth0
56: 879 0 GIC mmc0
72: 0 0 GIC pl330
73: 0 0 GIC pl330
74: 0 0 GIC pl330
75: 0 0 GIC pl330
82: 1382 0 GIC xuartps
91: 107 0 GIC observer
Only one signal is connected to PORT IRQ_F2P
The core generates only a pulse so the interrupt is configured for edge.
The kernel device tree parser adds #32
I find this quite strange and not well documented. However, I hope this helps people having the same problem.
Thanks and regards,
Marco
07-06-2015 06:03 AM
I have the same problem, but when I change the IROID from 61 to 29 ,it just can not be opened. Do you know the reason? Or can you tell me how to solve the problem which you met?
07-14-2018 10:58 PM
I have two extra interrupts that I added to the existent ones which mapped to :
64: 2 0 GIC 64 gpio1
65: 2 0 GIC 65 gpio2
from
amba_pl {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "simple-bus";
ranges;
gpio1@43c20000 {
#gpio-cells = <0x2>;
#interrupt-cells = <0x2>;
compatible = "generic-uio";
gpio-controller;
interrupt-controller;
interrupt-parent = <&intc>;
interrupts = <0x0 0x20 0x4>;
reg = <0x43c20000 0x10000>;
xlnx,all-inputs = <0x1>;
xlnx,all-inputs-2 = <0x0>;
xlnx,all-outputs = <0x0>;
xlnx,all-outputs-2 = <0x0>;
xlnx,dout-default = <0x0>;
xlnx,dout-default-2 = <0x0>;
xlnx,gpio-width = <0x3>;
xlnx,gpio2-width = <0x20>;
xlnx,interrupt-present = <0x1>;
xlnx,is-dual = <0x0>;
xlnx,tri-default = <0xffffffff>;
xlnx,tri-default-2 = <0xffffffff>;
};
gpio2@43c30000 {
#gpio-cells = <0x2>;
#interrupt-cells = <0x2>;
compatible = "generic-uio";
...
for example,
and when I insmod the IRQ drivers goes to
96: 0 0 zynq-gpio 0 int-test
97: 1 0 zynq-gpio 1 int-test2
and it is not firing the handler .