You still have to consider the irq remapping that's done in hardware. The PORT IRQ_F2P is a bus that's defined as (C_NUM_F2P_INTR_INPUTS-1) downto 0. If C_NUM_F2P_INTR_INPUTS=1, then you have port IRQ_F2P(0 downto 0)=chipscope_trigger.
Now, within the processing_system7 wrapper, since C_NUM_F2P_INTR_INPUTS is not 0 and is not 16, you will have the assignment:
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ, IRQ_F2P[(1-1):0], irq_f2p_null[(15-1):0]};
(Sorry, I'm mixing vhdl and verilog)
So in the end, the actual signals on the PS for irq_f2p are:
irq_f2p[19:0] = Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ, chipscope_trigger, 15'b0
So, with C_NUM_F2P_INTR_INPUTS=1, chipscope_trigger is actually on bit 15 of irq_f2p at the PS.
So SPI: Number 91.
Without testing, and using google, I would say:
interrupts = <0 75 4>
Google shows that 0=SPI, so the second number is the IRQ ID# of 91-16. If the first value was non-zero (private irq), then the calculated value would have been the IRQ ID# minus 32.
With the type=4, make sure the chipscope trigger is set as level high.
