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Observer
Observer
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Registered: ‎08-11-2018

Running Petalinux on an ARM+Microblaze design

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Guys,

           I'm working on a ZynqMPSOC design that requires both a microblaze and the ARM Cortex-A53. Both processors need to run a separate Petalinux image. My idea is to create two images using Petalinux SDK and place both of them on an SD Card. Then the A53 will execute its FSBL, and will do the following:

  • bring the microblaze(and the rest of the PL) out of reset
  • load its own linux image out of the SD card that is in a different DDR address space from that of the microblaze image. This can be done through u-boot load image commands to different DDR address offsets
  • Once the microblaze gets out of reset then it will execute from its proper image location in DDR. It will access the Zynq PS shared DDR through HP ports

         However, I'm missing the FSBL of the microblaze here. I don't think the microblaze can just start executing the linux image without running an FSBL for setup first. How would I have the microblaze FSBL on the SD card without it interfering with the A53's FSBL?

Thanks

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Observer
Observer
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Registered: ‎08-11-2018

Just bringing some closure to this thread....

The boot process I described earlier is spot on..., you just have the u-boot for the ARM load two different images to two different address spaces. You just have to make sure that you are writing the microblaze image to the reset vector of the microblaze as specified in the Vivado IDE microblaze IP block. Then, you need to compile the image to be raw binary. Due to some cross compile issues I had with petalinux sdk(never figured it out) I went the route of buildingrectly from git sources.

That takes care of that issue, the harder part is device tree gen. What you have to do is start with the device tree automatically generated byt the tools from the hdf, and then you will have to copy those items of the tree from the ARM PS dts that are used by the microblaze. It is not an automatic process at all since the tools are not smart enough to include PS items used by the PL in the device tree *even* if the microblaze has bus access to all of the PS's internal peripherals. Note that whatever PS peripherals you use in the microblaze dts must then be commented out in the PS ARM dts, otherwise you will have two different OS's trying to share peripherals and there will be trouble:D

So long story short, I got the ARM+Microblaze system working...

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Observer
Observer
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Registered: ‎08-11-2018

Bump..

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Highlighted
Observer
Observer
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Registered: ‎08-11-2018

Just bringing some closure to this thread....

The boot process I described earlier is spot on..., you just have the u-boot for the ARM load two different images to two different address spaces. You just have to make sure that you are writing the microblaze image to the reset vector of the microblaze as specified in the Vivado IDE microblaze IP block. Then, you need to compile the image to be raw binary. Due to some cross compile issues I had with petalinux sdk(never figured it out) I went the route of buildingrectly from git sources.

That takes care of that issue, the harder part is device tree gen. What you have to do is start with the device tree automatically generated byt the tools from the hdf, and then you will have to copy those items of the tree from the ARM PS dts that are used by the microblaze. It is not an automatic process at all since the tools are not smart enough to include PS items used by the PL in the device tree *even* if the microblaze has bus access to all of the PS's internal peripherals. Note that whatever PS peripherals you use in the microblaze dts must then be commented out in the PS ARM dts, otherwise you will have two different OS's trying to share peripherals and there will be trouble:D

So long story short, I got the ARM+Microblaze system working...

View solution in original post

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Visitor
Visitor
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Registered: ‎06-05-2018

Interested in your experience of the ARM+uBlaze design.

We have a similar design now in lab. The petalinux-2018.3 generated fsbl just hang, no move at all. 

Mind sharing your insights and ideas? Thanks.

Leon

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Observer
Observer
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Registered: ‎08-11-2018

Hey Leon,

                 Fighting some more Xilinx problems so in a bit of a crunch on time but maybe I can help. Where is it getting stuck? Is the FSBL on the microblaze on the ARM? Screenshot of where it is getting stuck might be helpful as well.

 

 

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Visitor
Visitor
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Registered: ‎06-05-2018

Thanks for offering help.

We originally have an Ethernet design with MicroBlaze which is doing a simple job of calibrating DDR. Then, we need to add an ARM core with it. The Cortex 53 is connected with the SAME DDR in PL via an Aix bus. The AXI bus works as an arbiter of all access to DDR.

Debug information is very limited. It seems failed at the first thing.

FSBL fails as the first line of "XFSBL_DDR_INIT_FAILED".
========= In stage err =======
Fsbl Error Status: 0x03

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Visitor
Visitor
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Registered: ‎06-05-2018
We fixed this bug.

FSBL 2018.3 added some code to re-initialize the DDR. But that wouldn't work on our board. So, I commented that out. This bug is fixed.

However, 2018.3 configuration has many other missed pieces, e.g. flash partitions. So, I used release 2018.2 release for now.

FSBL works, the bug is after u-boot, the Linux kernel boot hangs-out. Which we suspect u-boot didn't pass right parameters to the image.
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