UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor rajathrao78
Visitor
1,192 Views
Registered: ‎07-19-2018

SDK Memory Tests / Zynq DRAM Tests

Hello, 

 

I am new to Xilinx Sdk and I am booting my Xilinx Ultrascale + MPSoC from the SD Card. I want to include a Dram test template from Xilinx inside my boot.bin, The contents of my boot.bin are given below.

 

the_ROM_image:
{
[fsbl_config] a53_x64
[bootloader] fsbl.elf
[pmufw_image] pmuf.elf
[destination_cpu=a53-0, exception_level=el-3, trustzone] bl31.elf
[destination_cpu=a53-0, exception_level=el-2] ddr_test.elf
}

 

NOTE : ddr_test is the name of the default xilinx dram test template.

 

However, I am getting an error like this, "XFSBL_ERROR_ADDRESS" What am i doing wrong here?

error.PNG

0 Kudos
3 Replies
Contributor
Contributor
940 Views
Registered: ‎01-25-2018

Re: SDK Memory Tests / Zynq DRAM Tests

I've been trying to do the exact same thing and I suspect it's because the DRAM test template is supposed to run out of OCM.  FSBL currently runs out of OCM and there may be an issue with this.  By all means this is just my speculation.  I'm still waiting for an authoritative answer.

If you look at xfsbl_image_header.c: 

/**
* Not a valid address
*/
Status = XFSBL_ERROR_ADDRESS;
XFsbl_Printf(DEBUG_GENERAL,
"XFSBL_ERROR_ADDRESS: %llx\n\r", Address);

0XFFFC_0000 is the address of psu_ocm_ram_0, so the FSBL may be preventing the load from clobbering itself in memory.

0 Kudos
Xilinx Employee
Xilinx Employee
668 Views
Registered: ‎06-13-2018

Re: SDK Memory Tests / Zynq DRAM Tests

Hi @bkzshabbaz :

Your understanding is correct.

When you try to run DRAM test, the PS DDR-specific test linker script is intended to be run through on chip memoery (OCM).

But the FSBL loading also exists in OCM and FSBL is unable to overwrite itself with the DRAM test.

@rajathrao78 : It is recommended to run the DRAM memory test from JTAG.

 

Thanks,

Priyanka

------------------------------------------------------------------------------------------------

If you find any post has resolved your query, mark it as accepted solution.

0 Kudos
Xilinx Employee
Xilinx Employee
654 Views
Registered: ‎09-01-2014

Re: SDK Memory Tests / Zynq DRAM Tests

DRAM test needs to be running from JTAG boot mode.
In Jtag boot mode, the psu_init.tcl debug flow can no longer be used, the FSBL must be used to initialize the system during debug.
See following AR for the flow.
https://www.xilinx.com/support/answers/72210.html

0 Kudos