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Adventurer
Adventurer
7,462 Views
Registered: ‎11-05-2014

Setting FPGA clock rate

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When calling clk_set_rate() on the Zynq FPGA clocks (fclk0-3), which clk_ops are applicable?  I cannot tell in which file to find the ones that apply to the Zynq FPGA clocks. 

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Xilinx Employee
Xilinx Employee
14,430 Views
Registered: ‎03-13-2012

Re: Setting FPGA clock rate

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The gate and second divider both have the CLK_SET_RATE_PARENT flag (https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/zynq/clkc.c#n149), allowing a set_rate operation to walk up the clock tree. Hence, the set_rate operation will eventually operate on the divider clocks (https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/clk-divider.c).

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Xilinx Employee
Xilinx Employee
7,453 Views
Registered: ‎03-13-2012

Re: Setting FPGA clock rate

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That should not be too hard to trace through the code:

FCLK instantiation starts here: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/zynq/clkc.c#n365

 

Which leads to https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/zynq/clkc.c#n113, where the individual muxes, dividers and gates are instantiated.

 

The last one is the gate that is later exported as output from this module; https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/zynq/clkc.c#n158

 

clk_register_gate() assigns clk_gate_ops to its ops pointer (https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/clk-gate.c#n147), which is defined here: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/clk-gate.c#n107

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Adventurer
Adventurer
7,444 Views
Registered: ‎11-05-2014

Re: Setting FPGA clock rate

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I was trying to follow from the emacps driver calling clk_set_rate() here:

https://github.com/Xilinx/linux-xlnx/blob/f672c6bf89ae093b147e244f13d9e5886c5bfdbc/drivers/net/ethernet/xilinx/xilinx_emacps.c#L719

 

Then it calls clk_core_set_rate_nolock():

https://github.com/Xilinx/linux-xlnx/blob/f672c6bf89ae093b147e244f13d9e5886c5bfdbc/drivers/clk/clk.c#L1816

 

which calls clk_change_rate():

https://github.com/Xilinx/linux-xlnx/blob/f672c6bf89ae093b147e244f13d9e5886c5bfdbc/drivers/clk/clk.c#L1778

 

Then it walks a clock tree:

https://github.com/Xilinx/linux-xlnx/blob/f672c6bf89ae093b147e244f13d9e5886c5bfdbc/drivers/clk/clk.c#L1691

 

And calls clk->ops->set_rate() on each node:

https://github.com/Xilinx/linux-xlnx/blob/f672c6bf89ae093b147e244f13d9e5886c5bfdbc/drivers/clk/clk.c#L1723

 

This is where I get lost.  The clock tree I'm interested in is this one for Zynq's FPGA2 clock:

              fclk2_div0                   1            1   124999999          0 0
                 fclk2_div1                1            1   124999999          0 0
                    fclk2                  2            2   124999999          0 0

I added some debug messages and saw that set_rate() is only called for fclk2_div0 and stops there without calling set_rate on the children, but which set_rate() is the one for fclk2_div0?  The ones you pointed to are clk gate ops with enable/disable.  I'm looking for set_rate.

 

Thanks for your help.

 

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Xilinx Employee
Xilinx Employee
14,431 Views
Registered: ‎03-13-2012

Re: Setting FPGA clock rate

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The gate and second divider both have the CLK_SET_RATE_PARENT flag (https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/zynq/clkc.c#n149), allowing a set_rate operation to walk up the clock tree. Hence, the set_rate operation will eventually operate on the divider clocks (https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/clk-divider.c).

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