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Registered: ‎07-08-2019

Strange Ethernet auto-negotiation (100/1000Mbps) problem on custom zynqmp board

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Hi All - I'm looking for some pointers to get Ethernet auto-negotiation working properly on my custom board that is based upon the ZCU102.

  • It has GEM0 connected via MIO to a TI Phy (DP83867)
  • It supports speeds of 10/100/1000 Mbps...

For my basic test setup I have got the board connected to a gigabit switch, that also has my host PC connected (with both host PC and board negotiating a 1Gbps link). In U-Boot I have no problems using the Ethernet port at any speed and I can ping my host PC (and use TFTP to boot linux)

The operation in PetaLinux 2019.1 however is sketchy and depends upon what has happened previously in U-Boot. Cutting a long story short, If U-Boot does not use the Ethernet port (i.e. does not do a ping or TFTP and just boots Linux from NOR flash) I've noticed the following error being reported as Linux starts:

      zynqmp_clk_divider_set_rate() set divider failed for gem0_ref_ung_div1, ret = -22

Despite this error the macb driver does report it has a good ethernet link:

      macb ff0b0000.ethernet eth0: link up (1000/Full)

However, DHCP fails and even after directly setting an IP Address I cannot ping my host PC (or visa-versa)...

 

What I found was that the GEM0_REF_CTRL was not being updated with the required divisor values (given away by the zynqmp_clk_divider_set_rate() log message) - reading it with devmem gave a value of  0x06013C00, which will only work for a 100Mbps link; I verified this by running the following commands and pinging my host PC:

       ethtool -s eth0 advertise 0x0f           (limit auto-negotiation to 100Mbps only)

       /etc/init.d/networking restart           (restart networking)

If I use ethtool to revert back to gigabit auto-negotiation then communication once again stops:

       ethtool -s eth0 advertise 0x3f           (Allow auto-negotiation to support 100 and 1000Mbps)

... But if I use devmem to write updated divisors* directly to GEM0_REF_CTRL then communication (with a gigabit link) starts to work and I can ping my host PC:

       devmem 0xFF5E0050 32 0x60C0100

* (I got the register value by reading it in U-Boot after performing a ping)

I'm puzzled - why are these divisor values not being updated automatically in Petalinux-- ideas anyone?!

 

Thanks
Martin

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Registered: ‎09-12-2007

The HDF would only contain info on the IP, and not the IP itself.

 

However, you are correct. The TX clock should be 125Mhz. You will need to change this in vivado and re export to SDK to generate updated HDF

 

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Registered: ‎09-12-2007

Do you have the ccf enabled in your kernel settings:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841636/Common+Clock+Framework

 

 

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Registered: ‎07-08-2019

Yes; verified by running zcat /proc/config.gz | grep CONFIG_COMMON_CLK_ZYNQMP on the board:
      CONFIG_COMMON_CLK_ZYNQMP=y

Is there anything in the Vivado project / HDF that may have been missed regarding clocks (or the fact that this would be a reconfigurable clock to support 100Mbps and 1000Mbps?)?

 

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Registered: ‎09-12-2007

I dont think this is a HW issue since, manually setting the clocks in the register works for you.

What do you see when you do?

cat /sys/kernel/debug/clk/clk_summary

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Registered: ‎07-08-2019

I captured the output and attached it to this post. I did this once at initial boot (where Ethernet communication is not working) and then again after using the devmem 0xff5e0050 32 0x60c0100 command to tweak the divisors for 1 gigabit (verified Ethernet was working too)...

The files were identical - hence only attached 1 of the dumps... Looking at the clocks for gem0 I see 25Mhz features a lot, which is what I would expect for 100Mbps but this is a 1gigabit link...

I'm guessing but; Is it that the clock divisor driver can scale down a clock (from 125MHz to 25MHz) but not scale up (from 25MHz to 125Mhz) - i.e. should my vivado project default this to 125MHz not 25MHz?!

 

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Registered: ‎09-12-2007

Is your tx clk set to? this should be 125Mhz

 

Can you share the HDF?

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Registered: ‎07-08-2019

I'm not sure if I can attach the HDF as the design contains licensed 3rd party IP.... The psu_init.html file contains this about the clocks:

image.png

From what you're saying I'm guessing the GEM0 freq entry needs to be 125MHz (i.e. the highest supported speed of the interface)?

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Registered: ‎09-12-2007

The HDF would only contain info on the IP, and not the IP itself.

 

However, you are correct. The TX clock should be 125Mhz. You will need to change this in vivado and re export to SDK to generate updated HDF

 

View solution in original post

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Registered: ‎07-08-2019

@stephenm

Sorry for the delay in replying - the hardware guy has been off ill and I've only just got hold of an updated HDF...

I can confirm that setting the clock to 125MHz in the vivado project fixes the problem.

Thanks for your help & Support,
Martin

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