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Adventurer
Adventurer
139 Views
Registered: ‎09-19-2018

To modify addresses in system-user.dtsi

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Hi all,

I'm following this Xilinx' tutorial for creating a DPU based application and there's a moment that I have to add the DPU to the device tree.

And the tutorial says: 

At the bottom of project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi, add the following text:

&amba{
	dpu{
	    #address-cells = <1>;
    	    #size-cells = <1>;
    	    compatible = "xilinx,dpu";
    	    base-addr = <0x8F000000>;     //CHANGE THIS ACCORDING TO YOUR DESIGN
	    dpucore {
	        compatible = "xilinx,dpucore";
	        interrupt-parent = <&gic>;
	        interrupts = <0x0 0x59 0x4 >; //CHANGE THIS ACCORDING TO YOUR DESIGN
	        core-num = <0x1>; //CHANGE THIS ACCORDING TO YOUR DESIGN
	    };

/* Only enable this if softmax is added 
	    softmax { 
	        compatible = "xilinx,smfc";
	        interrupt-parent = <&gic>;
	        interrupts = <0x0 110 0x1>;
	        core-num = <0x1>;
	    };
*/
	};
};

As you can see I have change 3 addresses, but I don't know which addresses I have to place there.

Can anyone please give me some help into this issue?

Thanks in advance!!!

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Xilinx Employee
Xilinx Employee
58 Views
Registered: ‎10-06-2016

Hi @shairva 

The DPU address in your case is 0x80000000, that's the address that the PS (processors) needs to access to write in the DPU register space. The rest of addresses are the address the DPU can access within the system (DDR and OCM memories).

Regards


Ibai
Don’t forget to reply, kudo, and accept as solution.

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3 Replies
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Xilinx Employee
Xilinx Employee
94 Views
Registered: ‎10-06-2016

Hi @shairva 

The DUP IP is placed in your design in Vivado, so you need to get values from the Vivado design. If you are familiar with Vivado, you will realize that the base address is specified in the Address tab of the Block Design, and the interrupt number will depend on which PL-PS interrupt pin you connect the DPU interrupt signal.

Regards


Ibai
Don’t forget to reply, kudo, and accept as solution.
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Adventurer
Adventurer
63 Views
Registered: ‎09-19-2018

Hi @ibaie,

Thanks for your reply.

About the addresses, this is my Address tab:

address-tab

I generated those addresses automatically.

I'm a bit lost on this, and I really appreciate your help. What do you think is my dpu base-addr ?

Thanks in advance

 

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Xilinx Employee
Xilinx Employee
59 Views
Registered: ‎10-06-2016

Hi @shairva 

The DPU address in your case is 0x80000000, that's the address that the PS (processors) needs to access to write in the DPU register space. The rest of addresses are the address the DPU can access within the system (DDR and OCM memories).

Regards


Ibai
Don’t forget to reply, kudo, and accept as solution.

View solution in original post