cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer
Observer
293 Views
Registered: ‎07-31-2018

Two uio generation in zynq ZCU_102 device

Hello,

 

I am using the Xilinx CPRI IP in my design. I want to access the CPRI registers via zynq device so i generated an AXI wrapper using vivado "create and pack IP". I have some additional registers other than CPRI registers in my design and both the registers are in the same top module. I want two separate devices in the Linux for accessing these registers. So I replicate the AXI wrapper for two slaves and pack that IP. I got two separate AXI slave. I connect them to the zynq via AXI interconnect. After bitgen i import the hardware and generate the .hdf file. Now on PS side of the fpga .dts file is generated after build the project. I got the following entry as shown:-

 

amba_pl@0 {
#address-cells = <0x2>;
#size-cells = <0x2>;
compatible = "simple-bus";
ranges;

new_map_demap_axi_v1_0_cpri_and_user_reg_top@a0000000 {
compatible = "generic-uio";
reg = <0x0 0xa0000000 0x0 0x10000 0xa0010000 0x10000>;
xlnx,s00-axi-addr-width = <0xc>;
xlnx,s00-axi-data-width = <0x20>;
xlnx,s01-axi-addr-width = <0xc>;
xlnx,s01-axi-data-width = <0x20>;
};

 

In this entry only one base address is expose in Linux but inside this there are two separate register addresses as shown.

 

My question is how do i get two separate base addresses (two uio,s in Linux) ? or separate these two register addresses ?

 

I am attaching the block design and the axi wrapper files.

 

Thankyou

block_design.PNG
0 Kudos