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JPK17
Observer
Observer
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Registered: ‎03-11-2021

UART routed to PL via EMIO not working in Petalinux.

Hi all,

I am using zynq Arty-Z7-20 board. Vivado version v2020.2.

I have mentioned steps followed and shared my block design.

1. UART1 --> EMIO

2. UART1 TX [external] --> to pin Y18 (Arty-Z7-20)/JA PMOD, Pin 1 --> constraints file.

3. UART1 RX [external] --> to pin Y19 (Arty-Z7-20)/JA PMOD, Pin 2 --> constrainst file.

ie...

set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ja_r1 }];
set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ja_t1 }];

 

4. Synthesized/Implemented and Generated Bitstream with no issues

5. Export Hardware (including Bitstream).

6. Create petalinux project using zynq template.

7. When I build project without setting UART1 as EMIO no building error. 

8. After setting UART1 as EMIO on build project several time, I have got this error.

ERROR: [Common 17-55] 'get_property' expects at least one object.

 

What is the issue?

Screenshot from 2021-03-24 10-03-45.png


Thank you.

Regards,

JPK17

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