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Visitor mattyj207
Visitor
9,545 Views
Registered: ‎10-06-2015

UIO in Petalinux to access PL BRAM connected via AXI

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I have configured a very basic system consisting of a Zynq PS, a Block RAM and Controller, and a AXI interconnect. I had Vivado automatically make all the connections. I exported the hw to Petalinux 2015.2 and generated all the necessary files. I modified the device tree so that /dev/uio0 shows up when I boot up my microzed board. I can successfully open the uio0 file descriptor and mmap it.

 

The problem is when I go to do anything with the pointer returned from mmap. As soon as I try to read or write any address the OS locks up and I have to reboot. Is there some kind of initialization I'm not doing to "wake up" the axi interconnect or BRAM controller? Everything I have read indicates that once you have the memory mmaped you should be able to just use the pointer to acess anything in the range...but I must be missing something... Is the first bit of the range not addressable? I'm starting at 0 and only trying to access memory on 32 bit boundaries (0, 4, 8 ..etc)

 

Any advice would be much appreciated.

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Visitor mattyj207
Visitor
18,365 Views
Registered: ‎10-06-2015

Re: UIO in Petalinux to access PL BRAM connected via AXI

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Thank you! Your response lead me to check out this forum https://forums.xilinx.com/t5/Embedded-Linux/Can-access-PL-register-from-u-boot-but-not-petalinux/m-p/647827#M13844

 

I found that you were correct and my PL was the problem. For some reason petalinux disabled the clock to the PL by default in my pcw.dtsi file. I simply changed flclk-enable = <0x0> to flclk-enable = <0xf>. The clock was already enabled (flclk-enable = <0xf>) inside slcr in my zynq-7000.dtsi file.

 

Thank again!

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Xilinx Employee
Xilinx Employee
9,526 Views
Registered: ‎09-10-2008

Re: UIO in Petalinux to access PL BRAM connected via AXI

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Have you tried to use devmem from the console to access the memory?

I'm just wanting to make sure the PL is enabled and working and devmem should show you that.

The other good test is a baremetal (standalone) test from the Xilinx SDK.

Thanks
John
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Visitor mattyj207
Visitor
18,366 Views
Registered: ‎10-06-2015

Re: UIO in Petalinux to access PL BRAM connected via AXI

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Thank you! Your response lead me to check out this forum https://forums.xilinx.com/t5/Embedded-Linux/Can-access-PL-register-from-u-boot-but-not-petalinux/m-p/647827#M13844

 

I found that you were correct and my PL was the problem. For some reason petalinux disabled the clock to the PL by default in my pcw.dtsi file. I simply changed flclk-enable = <0x0> to flclk-enable = <0xf>. The clock was already enabled (flclk-enable = <0xf>) inside slcr in my zynq-7000.dtsi file.

 

Thank again!

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Xilinx Employee
Xilinx Employee
9,509 Views
Registered: ‎09-10-2008

Re: UIO in Petalinux to access PL BRAM connected via AXI

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In general the Linux kernel (Petalinux or not) disables the clocks for any unused device.  I have seen this in the AMP designs when Linux is not using the device and we remove it from the device tree because it's being used from a bare metal app on the other CPU.  I would have thought that the node in the device tree with UIO would have kept it from being disabled by Linux, but obviously not.  I'll have to watch out for more details on this one.

 

Thanks

John

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