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Visitor
Visitor
301 Views
Registered: ‎06-06-2020

UIO not detected - Petalinux 2019.1

Hello , 

Iam trying to communicate with a custom core withUIO Driver .First off, some info about my setup: 

iam using

- vivado 2019 

- Petalinux 2019.1 

- zynq Ultrascale+ MP

I Edited   <plnx_proj_root>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi so it looks like this:

chosen {
bootargs = "console=ttyPS0,115200 earlyprintk uio_pdrv_genirq.of_id=generic-uio";
};

};

&my_core_0 {

compatible = "generic-uio";

};

and from kerner configuration i enabled the UIO driver from userspace I\O drivers

yet i got errors

 1- When building my device tree that path my_core_0 not found

 

Subprocess output:
Error: build/tmp/work/plnx_zynqmp-xilinx-linux/device-tree/xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0/system-user.dtsi:130.1-16 Label or path my_core_0 not found
FATAL ERROR: Syntax error parsing input tree

 

 

2- I comment that lines and build to check bootargs , when i cat /proc/cmdline the output is 

earlycon console=ttyPS0,115200 clk_ignore_unused 

seems lime my args didn't applied

I followed alot of posts here but i couldn't find the answer , Am I missing any steps?

thank you , best regard.

 

 

 

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3 Replies
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Voyager
Voyager
275 Views
Registered: ‎08-02-2019

Hi @kholoud_amin ,

I'm using Petalinux 2018.2. It has major differences with 2019.1. I want to describe you how I'm working with uio driver without any problem.

I'm sure, this link belongs to Xilinx and it is well known link. 

It also contains instructions before and after 2019.

Maybe you need to check your FPGA design again. 

If you add a GPIO Ip Core in your FPGA design as mentioned in this link, then export hw, configure and build linux...

cp your_project_path/project_1/project_1.sdk/design_1_wrapper.hdf ../hwdef
petalinux-config --get-hw-description=../hwdef
petalinux-build
or to check only your device-tree is configured properly:
petalinux-build -c device-tree

 

Saban

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Highlighted
Visitor
Visitor
202 Views
Registered: ‎06-06-2020

hi @sabankocal  

Thank you , iam following the link and i am sure about my FPGA design i can find my core in the pl.dtsi 

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Highlighted
Visitor
Visitor
68 Views
Registered: ‎09-02-2020

Hi,

I have exactly the same problem. If I add a gpio and use it as uio It works. If I add my custom IP which is a interrupt generator I get the error message 

 

Subprocess output:
Error: /home/mselke/Working/Petalinux/build/tmp/work/zynqmp_generic-xilinx-linux/device-tree/xilinx-v2020.1+gitAUTOINC+bc84458333-r0/system-user.dtsi:14.1-24 Label or path PL_interrupt_generat_0 not found
FATAL ERROR: Syntax error parsing input tree

But the label is included in the generated pl.dtsi.

 

Have you solved the problem somehow?

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