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Explorer
Explorer
1,420 Views
Registered: ‎02-17-2017

Unable to configure spi to 5.5Mhz freq and how to avoid interbyte delay transfers in Linux version 4.9.0-xilinx-apf-g73402c0-dirty

Dear Xilinx experts,

 

 

I am facing lots of issues with spi driver in linux kernel version 4.9.0-xilinx-apf-g73402c0-dirty, could anybody please me, as I am stuck up with another issue, as all my development activites is going on 4.9.0 kernel, now i cant switch to any older kernel versions

 

After switching cpu freq to 333Mhz and having 0x00003F03 in 0xF8000158 spi transfers works fine with QSPI disabled in 4.9.0

 

But I want spi setup to be working with 5.5 Mhz without any interbyte delays, I even checked that the below registers output seems to be 0 for interbyte delays

devmem 0xE0006018
0x00000000

 

1. I am unable to get spi working with 5.5 clock freq, I check the spi_ref_clk_control register

 

devmem 0xF8000158
0x00003F03

 

devmem 0xF8000158 32 0x00000603 --> to achieve 5.5Mhz, am seeing the timeout issues,

 

Whereas I dont these issue in 4.6.0 kernel

 

2. I see interbyte delays between spi transfers as attached, even i dont these issue in 4.6.0 kernel

 

Could you please help me is there any workaround for the above two issues in 4.9.0 kernel?? am wandering that I would really get a fix for the above 2 issues,

 

Could anybody please take this as high priority in fixing this spi driver issues in 4.9.0 kernel, as many people in this forum are facing the same issue?

 

Kindly do the needful as early as possible

Eagerly awaiting for your replies

Many Thanks in advance

SPI_4Mhz_issue.png
Interbyte_delay_issue.png
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2 Replies
Explorer
Explorer
1,391 Views
Registered: ‎10-14-2015

Re: Unable to configure spi to 5.5Mhz freq and how to avoid interbyte delay transfers in Linux version 4.9.0-xilinx-apf-g73402c0-dirty

I think the proper way to change SPI settings is through the device tree and/or ioctl calls in your software application. I would avoid to talk directly to the hardware.

 

my I/O PLL clock is 166Mhz, I have managed to achieve 5.2MHz for my SPI_clock changing the max frequency in the device tree

 

&spi0 {
      is-decoded-cs = <0>;
      num-cs = <1>;
      status = "okay";
      bus-num = <0>;
      spidev0@0 {
        compatible="spidev";
        reg = <0>; //chipselect
        //spi-max-frequency= <1660000>; //old_frequency
        spi-max-frequency= <6640000>; //new_frerquency
        spi-cpha;
        bus-num = <0>;
    };

};

Regards,

Rocco

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Explorer
Explorer
1,389 Views
Registered: ‎02-17-2017

Re: Unable to configure spi to 5.5Mhz freq and how to avoid interbyte delay transfers in Linux version 4.9.0-xilinx-apf-g73402c0-dirty

May I know have u validated in 4.9.0 linux kernel version? , if so could u pls share me the system_top.bit, .vhd, .xdc and .vhd and fsbl

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