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Explorer
Explorer
199 Views
Registered: ‎12-20-2017

Using FPGA in 2018.2?

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In 2017.3, my process was to take the bitstream from the firmware engineer (using vivado 2017.2), and first put it into a BOOT.bin image to get programmed upon bootup, then to run bootgen on it to produce a .bit.bin file.   I would then update the firmware using the fpga manager at /sys/class/fpga_manager/fpga0/firmware using the procedures outlined here.

Under 2018.2, I'm able to flash the firmware from the bootable image, but I'm having issues with the firmware manager when trying to load the image created by the engineer (using 2018.1).  Specifically, it hangs.

root@tx_os:/application/firmware# cp file.bit.bin /lib/firmware

root@tx_os:/# echo 0 > /sys/class/fpga_manager/fpga0/flags
root@tx_os:/application/firmware# echo file.bit.bin > /sys/class/fpga_manager/fpga0/firmware [ 260.105459] fpga_manager fpga0: writing file.bit.bin to Xilinx ZynqMP FPGA Manager [ 293.413273] INFO: rcu_sched detected stalls on CPUs/tasks: [ 293.418688] 0-...: (1 GPs behind) idle=126/140000000000000/0 softirq=1632/1633 fqs=239 [ 293.426751] (detected by 1, t=5255 jiffies, g=227, c=226, q=2) [ 293.432652] Task dump for CPU 0: [ 293.435863] sh R running task 0 1860 1846 0x0000002e [ 293.442895] Call trace: [ 293.445332] [<ffffff8008085878>] __switch_to+0x98/0xb0 [ 293.450447] [<ffffffc877bee1c0>] 0xffffffc877bee1c0

 

(sometimes it gives me the above stall message... other times it just sits there forever)

I know everyone's answer is going to be to throw up their hands and say that I should not use mismatched versions of Xilinx products.  Maybe if it didn't require getting admin privs on a company computer and then having it take hours upon hours to install, we would have tried that already.  Plus, I have experience being one version off and it worked fine with 2017.3 and 2017.2.

 

What DOES work for me, however, is putting the image into a BOOT.bin:

 petalinux-package --boot --format BIN --fsbl images/linux/zynqmp_fsbl.elf  --u-boot images/linux/u-boot.elf --pmufw images/linux/pmufw.elf --force  --fpga file.bit
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Xilinx Employee
Xilinx Employee
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Registered: ‎04-15-2011

回复: Using FPGA in 2018.2?

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@aaron_b1 

How do you generate the bin file that is downloaded in Linux?

 

The bin file generation is different in 2017.x and 2018.x:

For Xilinx tools v2018.x :

bootgen -image Bitstream.bif -arch zynqmp -o ./Bitstream.bin -w

For Xilinx tools v2017.x & earlier:

bootgen -image Bitstream.bif -arch zynqmp -process_bitstream bin

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Xilinx Employee
Xilinx Employee
157 Views
Registered: ‎04-15-2011

回复: Using FPGA in 2018.2?

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@aaron_b1 

How do you generate the bin file that is downloaded in Linux?

 

The bin file generation is different in 2017.x and 2018.x:

For Xilinx tools v2018.x :

bootgen -image Bitstream.bif -arch zynqmp -o ./Bitstream.bin -w

For Xilinx tools v2017.x & earlier:

bootgen -image Bitstream.bif -arch zynqmp -process_bitstream bin

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Explorer
Explorer
133 Views
Registered: ‎12-20-2017

回复: Using FPGA in 2018.2?

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This appears to be the magic sauce.  thank you.

<rant>
What works in version 2017.X should work in 2018.X, and should work in the forseeable future. Backward compatibility should be high on the product priority list.  There is no reason that this command had to change its interface in such a way that it breaks preexisting usage.
</rant>

 

 

 

 

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