I set up a petalinux project which is based on zynq with a HLS IP , and develop app in vitis by using petalinux-build --sdk. My HLS IP uses m_axi interface to transfer some calculation and s_axilite to set some parameters. HLS IP does well in standalone vitis project by using Xil_DCacheDisable() (to get the data in DDR);. However, HLS IP can not perform well in Linux vitis project.
Here is the detail. I set up Linux vitis project(cpp project), and use hw functions which is created by vitis_hls and vitis to control my HLS IP(HLS IP is setted as the uio in Linux). It can set the right vaule in registers(some are relevant to s_axilite interface and some are relevant to m_axi interface )because I use function Get to check. However, I get zero output after starting my HLS IP. Does the m_axi interface can not function in Linux?(I use Xil_DCacheDisable() to get the right value output in standalone vitis project, so does it need to be used in Linux vitis project?)
