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Contributor
Contributor
10,968 Views
Registered: ‎02-24-2014

Using MIO interrupt from SPI slave

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Hi all

 

I am trying to connect an SPI-Ethernet controller (ENC28J60) to a 7C030 SPI0 in Petalinux 2015.2.

 

The kernel module successfully detects and initialises the chip but I haven't yet been able to get the interrupt to be detected. The interrupt line is connected to MIO31.

 

With the help of this post, I have specified the interrupt in the device tree and the driver seems to be happy with the settings (it is not slow in telling me if it is not!)

 

pcw.dtsi
...
&gpio0 {
 emio-gpio-width = <64>;
 gpio-mask-high = <0x0>;
 gpio-mask-low = <0x5600>;
};

 

 

system-top.dts
...

&gpio0 {
	#interrupt-cells = <2>;
	interrupt-controller;
};

&spi0 {
	compatible = "cdns,spi-r1p6";
	ethernet0: enc28j60@0 {
        #address-cells = <0x1>;
        #size-cells = <0x0>;
		compatible = "microchip,enc28j60";
		reg = <0>; /* CE0 */
		interrupt-parent = <&gpio0>;
		interrupts = <31 2>;	/* MIO 31, falling edge */
		spi-max-frequency = <20000000>;
		status = "okay";
	};
};

I can't see the interrupt count increasing when I insert the kernel module even though the physical interrupt line is going low as we'd expect.

 

 

root@ChameleonSFB_RegAccess:~# cat /proc/interrupts
           CPU0       CPU1
 16:          0          0       GIC  27  gt
 17:          0          0       GIC  43  ttc_clockevent
 18:       1615       2793       GIC  29  twd
 21:         43          0       GIC  39  f8007100.adc
 54:          0          0  zynq-gpio  31  enc28j60
141:          0          0       GIC  80  cdns-i2c
142:          0          0       GIC  35  f800c000.ocmc
143:       1662          0       GIC  59  xuartps
144:        680          0       GIC  58  e0006000.spi
145:          0          0       GIC  51  e000d000.spi
146:          0          0       GIC  45  f8003000.dmac
147:          0          0       GIC  46  f8003000.dmac
148:          0          0       GIC  47  f8003000.dmac
149:          0          0       GIC  48  f8003000.dmac
150:          0          0       GIC  49  f8003000.dmac
151:          0          0       GIC  72  f8003000.dmac
152:          0          0       GIC  73  f8003000.dmac
153:          0          0       GIC  74  f8003000.dmac
154:          0          0       GIC  75  f8003000.dmac
155:          0          0       GIC  40  f8007000.devcfg
IPI1:          0          0  Timer broadcast interrupts
IPI2:       1974       1949  Rescheduling interrupts
IPI3:          0          0  Function call interrupts
IPI4:         20         32  Single function call interrupts
IPI5:          0          0  CPU stop interrupts
IPI6:          0          0  IRQ work interrupts
IPI7:          0          0  completion interrupts
Err:          0

 

 

Questions:

  1. Is it enough to specify the MIO pin as an interrupt for it to be set up correctly (GPIO direction etc.)?
  2. Do I need to specify a pinctrl type entry such as in this dtsi?
  3. I can't seem to do the usual "export 31 > /sys/class/gpio/export" so does that mean my project generation isn't correct?

 

As always, any help is greatly appreciated.

Chris

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Xilinx Employee
Xilinx Employee
20,753 Views
Registered: ‎09-10-2008

Re: Using MIO interrupt from SPI slave

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Hi Chris,

 

I attached the patch I used for testing.  Please consider this to be a temporary patch that will get you out of sync with the Xilinx kernel such that you should watch for something else in the tree and then get back in sync.  I can't guarantee this is the patch that will make it into the tree but it fixed my issue. 

 

Thanks

John

11 Replies
Xilinx Employee
Xilinx Employee
10,956 Views
Registered: ‎09-10-2008

Re: Using MIO interrupt from SPI slave

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Hi Chris,

I just went thru this a couple weeks ago for a SPI device and had a similar issue. The examples others did which were working were different interrupt trigger levels. I found the PS GPIO driver had an issue that had to be corrected to make this work for other interrupt trigger types. When I looked at the GPIO registers after the kernel booted they were not setup correctly to produce the interrupt. When I manually setup the registers using devmem then the interrupt started working.

http://www.wiki.xilinx.com/Device+Tree+Tips

There is a patch for this GPIO driver issue but it's not in the tree yet that I can find. I'll ask about it and get back to you on it.

Thanks
John
Highlighted
Xilinx Employee
Xilinx Employee
20,754 Views
Registered: ‎09-10-2008

Re: Using MIO interrupt from SPI slave

Jump to solution

Hi Chris,

 

I attached the patch I used for testing.  Please consider this to be a temporary patch that will get you out of sync with the Xilinx kernel such that you should watch for something else in the tree and then get back in sync.  I can't guarantee this is the patch that will make it into the tree but it fixed my issue. 

 

Thanks

John

Xilinx Employee
Xilinx Employee
10,948 Views
Registered: ‎09-10-2008

Re: Using MIO interrupt from SPI slave

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I should have said that this worked for Petalinux 2015.2 3.19 kernel. The pin control stuff you mention above looks like it's in a newer kernel and I've not had to go there yet.
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Contributor
Contributor
10,938 Views
Registered: ‎02-24-2014

Re: Using MIO interrupt from SPI slave

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Thanks, John. I'll give it a try.

Chris

 

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Contributor
Contributor
10,927 Views
Registered: ‎02-24-2014

Re: Using MIO interrupt from SPI slave

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Hmm. Still no joy.

Just to confirm, I applied the patch to /opt/pkg/petalinux-v2015.2-final/components/linux-kernel/xlnx-3.19/drivers/gpio/, cleaned and rebuilt the image and booted by board via JTAG.

 

I had previously tried to check the GPIO registers using devmem but couldn't seem to read them correctly. Reading back DATA_0_RO in the GPIO section from U-boot and Petalinux I get the following. (I'm interested in MIO31.)

 

U-Boot-PetaLinux> md 0xE000A060
e000a060: fff0fe01 003c18ff 00000000 00000000 ......<.........

 

# devmem 0xE000A060
0x00000000

 

I thought I could read the absolute address since devmem remapped it for me.

 

Chris

 

 

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Xilinx Employee
Xilinx Employee
10,922 Views
Registered: ‎09-10-2008

Re: Using MIO interrupt from SPI slave

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you are reading the registers with devmem, Linux is hosing them up after u-boot runs, that's the issue.
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Xilinx Employee
Xilinx Employee
10,922 Views
Registered: ‎09-10-2008

Re: Using MIO interrupt from SPI slave

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Chris, are you sure it got a new version of the kernel from the install? Likely so after the clean, but a mrproper might be needed, I don't remember for sure. I typically create a local kernel in the components of the project and patch it rather than hacking on the install kernel, but what you did will work.
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Contributor
Contributor
10,914 Views
Registered: ‎02-24-2014

Re: Using MIO interrupt from SPI slave

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Hi John

 

Kernel patching is new to me but I did do an mrproper on the build so that should have picked it up, right?

 

As a update, I tried changing the interupt to active low instead of falling edge.

 

 

interrupt-parent = <&gpio0>;
interrupts = <31 8>; /* MIO 31, active low */

 

Now the interrupt does trigger and the count in /proc/interrupt increases! Not sure if there is still an issue with a falling edge in my configuration even beyond your patch.

 

 

Setting a static address for eth0 and restarting the network interfaces brings up my link and my board now responds to pings!

 

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Contributor
Contributor
10,908 Views
Registered: ‎02-24-2014

Re: Using MIO interrupt from SPI slave

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Any ideas why a falling edge interrupt still fails?

 

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Xilinx Employee
Xilinx Employee
7,843 Views
Registered: ‎09-10-2008

Re: Using MIO interrupt from SPI slave

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:) I only tested leading edge as that was what my system was. It's likely a GPIO setup issue but I'm not sure. I've got other stuff I'm trying to work on right now so I've not got time to look at it. You're getting closer.
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Contributor
Contributor
7,836 Views
Registered: ‎02-24-2014

Re: Using MIO interrupt from SPI slave

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Not to worry. I'm taking a tentative win since the driver responds to the active low level :)

 

Once again, thanks for your assistance, John.

Regards

Chris

 

 

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