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simon_tam_gmail
Contributor
Contributor
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Registered: ‎08-20-2019

VCU TRD HDMI RX Pipeline modification

Hi,

   The current VCU TRD HDMI RX capture pipeline described in UG1250 is like the following:

VPhy->HDMI_RX_SS->VPSS->Frmbuf->HP (ZynqUltra PS)

   I like to modify this pipeline to split off a stream before the VPSS as follow:

VPhy->HDMI_RX_SS->broadcast->VPSS->Frmbuf->HP (ZynqUltra PS)

   During the build I got the following error message (excerpt)

ERROR: [Hsi 55-1545] Problem running tcl command ::sw_vproc_ss::generate : can't read "hdmi_ports_node": no such variable
| while executing
| "add_or_get_dt_node -n "port" -l vpss_port1 -u 1 -p $hdmi_ports_node"
| ("foreach" body line 18)
| invoked from within
| "foreach connected_out_ip $connect_out_ip {
| if {[llength $connected_out_ip] != 0} {
| set connected_out_ip_type [get_property IP_NAME $connected_out..."
| (procedure "::sw_vproc_ss::generate" line 114)
| invoked from within
| "::sw_vproc_ss::generate hdmi_input_v_proc_ss_0"
| ERROR: [Hsi 55-1442] Error(s) while running TCL procedure generate()
| hsi::generate_target: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 871.910 ; gain = 10.121 ; free physical = 1894 ; free virtual = 11337
| generate_target failed
| while executing
| "error "generate_target failed""
| invoked from within
| "if {[catch {hsi generate_target -dir $project} res]} {
| error "generate_target failed"
| }"

   From what I can gather it is not allowed to break the connection between the HDMI_RX_SS and VPSS based on the existing software architecture. Here are my questions:

1. Is it even feasible to insert a broadcaster (or any IP for that matter) in between the HDMI_RX_SS and VPSS?

2. If yes how do I go about making it work in the build?

 

Thanks,

 

Simon

 

 

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10 Replies
florentw
Moderator
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709 Views
Registered: ‎11-09-2015

HI @simon_tam_gmail 

  1. What version are you using?
  2. Can you generate the HDF/XSA?
  3. Yes it is feasible to insert a broadcaster (or any IP for that matter) in between the HDMI_RX_SS and VPSS but will not be straight forward both to generate the device tree and to run under v4l2
  4. To make the build working, build the components individually. Here it is the device tree generation which is failing. Just build the device tree manually based on the device tree from the VCU TRD

Florent
Product Application Engineer - Xilinx Technical Support EMEA
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simon_tam_gmail
Contributor
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Registered: ‎08-20-2019

Hi Florentw,

    Thanks for the reply. Please see below:

  1. I am using Vivado/Petalinux 2019.2
  2. The XSA file is attached.
  3. Can you elaborate what may be the problem running under v4l2 assuming I manually generate a working dts?
  4. I can give that a try.

   In my humble opinion, I am not the first and last customer wanting to split a video stream from the HDMI_RX capture pipeline. Can Xilinx give an example or provide enough info so someone can follow how to do it properly?

Thanks,

 

Simon

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florentw
Moderator
Moderator
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Registered: ‎11-09-2015

Hi @simon_tam_gmail 

I like the fact that your xsa is called Tahiti. It reminds me my holiday 2 weeks ago

With that said, could you upload your xsa again. It seems corrupted. I cannot open it with the tools.

  1. Can you elaborate what may be the problem running under v4l2 assuming I manually generate a working dts?
    [Florent] - I am not sure what is supported by the drivers depending on what you do. V4l2 devices usually have a single endpoint connections

 In my humble opinion, I am not the first and last customer wanting to split a video stream from the HDMI_RX capture pipeline. Can Xilinx give an example or provide enough info so someone can follow how to do it properly?

[Florent] - There is multiple things here. It is much easier to do it with baremetal because there is less limitations from the drivers. But this is more a limitation of the v4l2 subsystem

The VCU TRD 2019.2 should have an example if you look at the multi-stream design https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/176652339/Zynq+UltraScale+MPSoC+VCU+TRD+2019.2+-+VCU+TRD+Multi+Stream


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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simon_tam_gmail
Contributor
Contributor
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Registered: ‎08-20-2019

Hi Florentw,

   Tahiti is my dream vacation spot. I envy you could spend holiday there. (My other project is called BoraBora btw.) I attached the .xsa file which shows the original problem of having a broadcaster in between RXSS and VPSS. 

   Not sure I mentioned If I split the video stream after the VPSS then the whole thing works meaning that the capture pipeline and the gst recording application work. It seems the framework does not mind extra output in the existing broadcaster. In the case of RXSS->Broadcaster->VPSS I am hoping after manually editing the dts the capture framework will continue to work. 

   And for the custom part of my design did you suggest I should go baremetal rather than to make use of the existing Xilinx Linux drivers? When you say baremetal do you mean doing it through the UIO device driver?

thanks,

Simon

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watari
Teacher
Teacher
623 Views
Registered: ‎06-16-2013

Hi @simon_tam_gmail 

 

I just ask you the following.

Do you have HDMI Rx IP's license ?

 

If no, it might be the route cause...

 

Best regards,

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simon_tam_gmail
Contributor
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Registered: ‎08-20-2019

Hi Watari,

   Yes I do have the HDMI RX/TX_SS license. As you may know most other video IPs don't require licenses anymore.

thanks,

Simon

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watari
Teacher
Teacher
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Registered: ‎06-16-2013

Hi @simon_tam_gmail 

 

Which OS are you using on Vivado ?

If OS is Windows10, it might be path length issue.

If yes, I suggest you to use Vivado on linux...

 

Best regards,

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florentw
Moderator
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Registered: ‎11-09-2015

Hi @simon_tam_gmail 

The good point with naming your projects as per onw of the french Polynesian island is that there a 118 islands so you have a lot of names for you future project

The new xsa you attached is still not working for me. There are still missing pieces inside

And for the custom part of my design did you suggest I should go baremetal rather than to make use of the existing Xilinx Linux drivers? When you say baremetal do you mean doing it through the UIO device driver?

Well, if this is working for you then it is fine. But the linux drivers are not fully tested for multiple chains so I am not exactly sure how they will behave


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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simon_tam_gmail
Contributor
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Registered: ‎08-20-2019

Hi Florentw,

   Sorry I did not reply earlier. I was busy as you can imagine. I have the correct XSA file attached. Regarding your recommendation to build components separately I am not sure which component(s) I should skip to bypass the DTG. Do you have more information on how to manually build the kernel to avoid this problem?

thanks,

Simon

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clivewmwalker
Adventurer
Adventurer
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Registered: ‎03-21-2013

Hi Simon, Florent.

I read your forum post. I think Tahiti would be a very nice place to be quarantined.....

Anyway. I am trying to do something similar to you. Did you manage to get it going? If so, would you be willing to share the device-tree syntax?

In my case, I need to use a broadcaster to take the output of HDMI RX to 2 destinations (in fact one destination is a VPSS, and the other is a v_frmbuf_wr). I recognize that there's no device-tree entry for a broadcaster, and that I can use multiple endpoints for a port - so here was my best guess for the RX:

   ch1_hdmirx_port: port@0 {
      reg = <0>;
      ch1_vcu_hdmi_rx_out: endpoint@0 {
         remote-endpoint = <&ch1_v_proc_csc_in>;
      };
      ch1_passthru_hdmi_rx_out: endpoint@1 {
         remote-endpoint = <&multichan_proc_vcap_hdmi_in>;
      };
   };

Unfortunately, this didn't work. I'm not sure why yet - hence my interest in your outcome.

Thanks for any help

I have attached pl.dtsi and system-user.dtsi files if anyone feels so inclined.....

Clive

 

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