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nvl1109
Adventurer
Adventurer
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Registered: ‎06-14-2018

VDMA fsyncsrc in CR register

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Hi all,

I'm confusing that the FSYNCSRC bits isn't consistence between Linux VDMA driver and the manual document (PG020).

The driver code using bit[5:6] for FSYNCSRC, but the PG020 said these bits are reserved.

Code: https://github.com/Xilinx/linux-xlnx/blob/master/drivers/dma/xilinx/xilinx_dma.c#L74

Manual :

 Selection_007.png

 

So which is correct? Thank you. 

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radheys
Xilinx Employee
Xilinx Employee
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Registered: ‎02-20-2014

In earlier IP versions this field was used to runtime configure FsyncSrcSelect. See https://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v5_00_a/pg020_axi_vdma.pdf

 

In the new IP version, the fsync option is IP customization parameter (no more runtime programmable). 

Hope that helps.

 

Thanks,

Radhey

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radheys
Xilinx Employee
Xilinx Employee
481 Views
Registered: ‎02-20-2014

In earlier IP versions this field was used to runtime configure FsyncSrcSelect. See https://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v5_00_a/pg020_axi_vdma.pdf

 

In the new IP version, the fsync option is IP customization parameter (no more runtime programmable). 

Hope that helps.

 

Thanks,

Radhey

View solution in original post

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