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Adventurer
Adventurer
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Registered: ‎05-04-2018

VxWorks 7 ZCU102 PS UART 1

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I am using a ZCU102 board and have a Vivado design that routes the PS UART 1 to EMIO pins on my FMC breakout board. In VxWorks 7 I can only get the read() function to accept input from my keyboard when typing into the bridge interface 1 (you can see this for CP210x in device manager). It does not register anything on the pin. I can successfully transmit via a pin (this also sends it to the terminal as well). How can I only route input/output from pins and not to/from my keyboard?

 

As a side note, I'm somewhat familiar with VxWorks' driver system as I wrote a driver for PS SPI and AXI Quad SPI that both worked. I have also used the provided ns16550 drivers with the AXI 16550 UART externally and this was able to read() and write() successfully. 

 

I suspect something is lost in translation between Vivado and Workbench (VxWorks' IDE) such as psu_init.c or other config files as VxWorks only requires a bin file for hardware as opposed to an HDF file. If there is anyone here who has knowledge on the BSP for the ZCU102 or even a Zynq 7000 that could help me with this issue I would very much appreciate it.

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Adventurer
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Registered: ‎05-04-2018

Re: VxWorks 7 ZCU102 PS UART 1

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@katsuki 

 

Thank you for responding. I created my own custom FSBL instead of using the prebaked one and it solved my issue of being able to receive external data from a pin. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-05-2019

Re: VxWorks 7 ZCU102 PS UART 1

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Hello,

This my post may not be the solution.


The MPSoC PS-UART0 and PS-UART1 of ZCU102 are connected to J83 (Micro USB Connector) via CP2018.

- Have you verified that there is no problem with this default connection?

- Of course, if EMiO is used, the PL must be configured.

- Are there any problems with the FMC card power supply or wiring connection?

 

If there are no problems, I think that the settings are for VxWorks's IDE.

 

Thanks,

Yoichi

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Adventurer
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Registered: ‎05-04-2018

Re: VxWorks 7 ZCU102 PS UART 1

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I have attached my block diagram and constraints below. I believe it is correctly wired up, but somehow the registers in the ZCU102 are telling it to use MIO 20 and 21 via CP2108 regardless of my hardware design being EMIO. 

Vivado Block Design.PNGUART Constraints.PNG

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-05-2019

Re: VxWorks 7 ZCU102 PS UART 1

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Hello

 

I don't know the flow using VxWORKS, so it may not be relevant, but is the following helpful?

 

Xilinx Using VxWorks BSP with Zynq-7000 AP SoC (XAPP1158)
https://www.xilinx.com/support/documentation/application_notes/xapp1158-zynq-7000-vxworks-bsp.pdf


VxWorks 7 BSP for Xilinx ZCU102
https://bsp.windriver.com/index.php?bsp&on=details&bsp=13282

 

BTW, PS settings are included in FSBL, so I think FSBL is necessary for VxWORKS flow.

 

Thank you

Yoichi

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Adventurer
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Registered: ‎05-04-2018

Re: VxWorks 7 ZCU102 PS UART 1

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@katsuki 

 

Thank you for responding. I am currently using that VxWorks BSP you listed. This does include the UART driver and the UART driver is functional. It just will not route via EMIO as opposed to its default routing through the MIO. This only allows me to use it as a serial terminal. I want to use it on the wire.

Regardless of VxWorks (which only takes a bin file from Vivado), how would I go about setting up Ultrascale registers and such in the FSBL? I saw the document you linked but this is for the Zynq-7000. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-05-2019

Re: VxWorks 7 ZCU102 PS UART 1

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Hi, @doverstreet6 


It seems that there is a dedicated flow on VxWORKS side.

I think it's better to contact WindRevier.

 

Thank you

Yoichi

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Adventurer
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Registered: ‎05-04-2018

Re: VxWorks 7 ZCU102 PS UART 1

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@katsuki 

 

Thank you for responding. I created my own custom FSBL instead of using the prebaked one and it solved my issue of being able to receive external data from a pin. 

View solution in original post