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Registered: ‎02-05-2018

WARNING: Will not program bistream on the target - rename bitstream file

Because the following post was "solved", I cannot post to it anymore.


Here is the response I was trying to post.


@Anonymous... Simply put... you are amazing. I don't know why anyone else on here hasn't marked this as the solution. I do not understand why this works, but doing just as you said makes the "FPGA DONE" light on my PicoZed Carrier Card gen2 light up.

Unfortunately, the kernel still does not boot, but I'll post that as a separate question.


Dear Xilinx...


I'm using the step on page 28 of the v2017.4 ug1144 (Dec 20, 2017):


petalinux-package --prebuilt --fpga /home/me/dev/petalinux_projects/my_project_name/images/linux/system_wrapper.bit

You need to recognize this issue! The warning message that we are encountering must be old because:

  1. It contains a typo "prebuitl".
  2. It recommends using the --bitsream option, which does not exist for the petalinux-package --prebuilt.  Digging around I discovered it's supposed to refer to the petalinux-boot command instead.

And then add in the response by @Anonymous about having to rename the system_wrapper.bit to download.bit... why does this work and why will it not work with the original bitstream name?


$ petalinux-boot --jtag --prebuilt 3
WARNING: Will not program bitstream on the target. If you want to program bitstream,
WARNING: please run petalinux-package --prebuilt to put the bitstream to the prebuitl directory,
WARNING: or use --fpga --bitstream option to specify a bitstream.
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Registered: ‎09-12-2007

when you run petalinux-boot --jtag.. This is using a XSCT tool and a script to to boot the linux, similar to the script below (this is for Zynq Ultrascale). So, Im guessing that the script being used is expecting the bit file to be called download.bit. You can verify this in the script that is generated


petalinux-boot --jtag --tcl log.txt


Check the fpga command used here to see what file name it expects..



targets -set -filter {name =~ "MicroBlaze PMU"}
dow pmufw.elf
targets -set -filter {name =~ "PSU"}
fpga -f download.bit
# disable isolation for PL
mask_write 0XFFD80118 0x00800000 0x00800000
mask_write 0XFFD80120 0x00800000 0x00800000
# write bootloop and release A53-0 reset
mwr 0xffff0000 0x14000000
mwr 0xFD1A0104 0x380E
exec sleep 1
# download and run FSBL
targets -set -filter {name =~ "Cortex-A53 #0"}
# downloading FSBL
dow zynqmp_fsbl.elf
after 500
dow -data image.ub 0x80000
dow u-boot.elf
dow bl31.elf

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