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kevin.jesse
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Registered: ‎02-16-2015

WARNING: Will not program bitstream on the target

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Hi Guys,

 

Even after running

 

[root@localhost test]# petalinux-package --prebuilt --fpga ./subsystems/linux/hw-description/base_zynq_design_wrapper.bit
INFO: Pre-built directory is updated.

 

I still can't get the bitstream on the board and it hangs at Petalinux boot hangs on: 'Waiting for PHY auto negotiation to complete..'

 

Is the bitstream getting put on the board? Is the processor just stopped. I tried starting it as suggested here,

 

http://forums.xilinx.com/t5/Embedded-Linux/Petalinux-boot-hangs-on-Waiting-for-PHY-auto-negotiation-to/m-p/475328#M9489

 

but with no such luck. My console output is below

 

Thanks,

Kevin

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kevin.jesse
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Registered: ‎02-16-2015

My solution was to use the BSP and import my project rather than using an empty zynq project.

 

Kevin

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vijayak
Xilinx Employee
Xilinx Employee
7,514 Views
Registered: ‎10-24-2013
Hi,
Moving to Embedded linux board.
Thanks,Vijay
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kevin.jesse
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Registered: ‎02-16-2015

Any followup on this? I'm sure someone has been able to get a vivado project to compile with petalinux AND program the bitstream to the board. What could I be doing wrong??

 

Kevin

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rfs613
Scholar
Scholar
7,396 Views
Registered: ‎05-28-2013
Hi Kevin,

There can be many possible causes, but the most common one is having devices listed in the device tree (DTS) which are not actually present. The best way to debug is to enable earlydebug, or alternatively, you can read the kernel log manually via JTAG tools. The steps for the latter are explained here: http://www.wiki.xilinx.com/Debugging+PowerPC+Kernel+Boot+Problems (even though it is for PowerPC, the same process applies on Zynq. You are basically looking for address of the log_buf symbol, and dumping out the memory at that location).

Before resorting to that, I would suggest you try booting with a "minimal" DTS for your board. If you are based of a reference design, try the DTS that came with it, and comment out any of the non-essential peripherals. In particular you might leave out the ethernet interfaces initially. Once you get it booting (or some form of output after "Decompressing linux..." then you can start adding back in devices).

-R
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kevin.jesse
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Registered: ‎02-16-2015

My solution was to use the BSP and import my project rather than using an empty zynq project.

 

Kevin

View solution in original post

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Anonymous
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@kevin.jesse wrote:

My solution was to use the BSP and import my project rather than using an empty zynq project.

 

Kevin


Just rename the bit-stream filename to download.bit, it will work well;

e.g. : if you generate a bitstream file design_wrapper.bit in Vivado, you should modify its name (download.bit) under the directory "pre-built/Linux/implementation"

eliezer
Explorer
Explorer
770 Views
Registered: ‎03-21-2019

Why does the name of the bitstream matter?

smahalle
Xilinx Employee
Xilinx Employee
731 Views
Registered: ‎09-17-2019

No need to change bitstream name

Thanks,

Shubhangi

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lperera
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Registered: ‎06-17-2020

I had the same problem,Renaming the bitstream to download.bit solved the problem. I am using petalinux 19.2

details:

I packed using

petalinux-package --prebuilt --fpga    / .  .  . /project_1/project_1.runs/impl_1/design_1_wrapper.bit

thendid a  JTAG boot:

petalinux-boot --jtag --prebuilt 3

 

This was giving a WARING : Will not program bitstream on the target. If you want to program bitstream, please run petalinux-package --prebuilt to put the bitstream to the prebuitl directory,

renamed pre-built/linux/implementation/design_1_wrapper.bit  to download.bit

Now no warnings and FPGA is programmed in boot up.

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aivchenko
Visitor
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Registered: ‎12-06-2019

The same thing happens in 2020.1.1

Need to "cp ./pre-built/linux/implementation/my_bitstream.bit ./pre-built/linux/implementation/download.bit" then it is loaded into FPGA

 

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