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861 Views
Registered: ‎09-10-2018

Warnings with generated with pl.dtsi with dtc 1.5

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I am currently trying to build a device tree overlay for a FPGA design.  I want to be able to load this image dynamically thought the fpga_manager.  and I'm following the steps from the Solution ZynqMP PL Programming page at

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841847/Solution+ZynqMP+PL+Programming

I'm running the 2018.3 version of petalinux and Vivado and I am runing on a MicroZed 7020 board from Avnet.

The main interest in the overlay is to be able to use the Xilinx DMA drivers from a linux kernel driver. There are a few other devices in the tree that I would like to remove later, but I was hoping to get this working without hacking on it too much fisrt. 

So I build the dtc version 1.5 on a centOS 7.x machine (the device tree binary format is the same for x86 and ARM so I don't need to build it with a cross-compile ?? (that is a question to confirm)).

Then I get a bunch of errors.. And when I try to load the overlay on the target machine the kernel spits out this error on the console.

OF: resolver: no symbols in root of device tree.

OF: resolver. overlay phandle fixup failed: -22

create_overlay: Failed to resolve tree

Any idea what might be going on, or where I made a mistake ?

Attached are the HDF and pl.dtsi files that are generated

 

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Registered: ‎09-10-2018

Re: Warnings with generated with pl.dtsi with dtc 1.5

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So I figured out what the errors were with the dtc compile.  It was confused about the address-cells and size-cells values.. It was complaining that the address was not a 64 bit number. (and on the zynqmp I'm sure it puts out 64 bit addresses and works).  So I added the #address-cells = <1>; and #size-cells = <1>; to the dtsi file and it was happy.

It was also complaining about the dma-channel@40400030 {} block having a name but not a reg ?  probably not needed as the driver probably assumes this information anyway.  But I added a reg = <0x40400030 0x20> and that made it happy.

It might be worth filing a bug against whatever generates these patterns for the overlays.  In the normal device-tree I think it would inherit the value from the parent.. but with the overlay I'm not sure how dtc resolves that (or if it even can).

So got it loading and now to see if it actually works :)

 

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Registered: ‎09-10-2018

Re: Warnings with generated with pl.dtsi with dtc 1.5

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Oh.. and it would be nice if the next petalinux distribution could have an up to date dtc that supports overlays :)
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Registered: ‎09-12-2007

Re: Warnings with generated with pl.dtsi with dtc 1.5

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Yes, Unfortunately symbol support is only supported after 1.4.3 dtc I believe. I use 1.5.0 dtc, and add this to my path.

I attached a helper_proc.tcl that you can use in XSCT that will run the devicetree generator (with overlays enabled), and will compile

in dtc to create the pl.dtbo. You can also use the script to convert your bit to bit.bin file too.

 

for example source this in XSCT, and run the commands below:


generate_dts <path to hdf>.hdf
bit2bin <path to bit>.bit

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Registered: ‎09-12-2007

Re: Warnings with generated with pl.dtsi with dtc 1.5

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Regarding your error, can you open the petalinux-config -> DTG settings -> devicetree flags "-b 0 -@"

 

For example:

dtg_settings.png

 

Also, you can disable the PL devicetree if you wish. This is the flow I do use as I program the PL over TFTP and not via the FSBL (No bit in the 

boot.bin file)

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Registered: ‎09-10-2018

Re: Warnings with generated with pl.dtsi with dtc 1.5

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So I tried your generate_dts script with one modification that I'm using a zynq-7020, so I changed the processor to a ps7_cortexa9_0 and I staill get the same error output as I posted before.

I notice that most of the instructions I have seen are using the Zynq UltraScale processors as their examples, and I'm wondering if there might be some bugs lurking around in the Zynq-7000 space?

 

And you give my hdf file a try and see if you get the same errors.?

 

I'm using petalinux to generate the pl.dtsi file in the components/plnx_workspace/device-tree/device-tree directory in my petalinux build.

And this is using the 2018.3 Vivado (with SDK) and petalinux tool chains

 

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Registered: ‎09-12-2007

Re: Warnings with generated with pl.dtsi with dtc 1.5

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I have only tries this on a zynq ultrascale and rfsoc. Not on a zynq 7000.

 

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Registered: ‎09-10-2018

Re: Warnings with generated with pl.dtsi with dtc 1.5

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So I figured out what the errors were with the dtc compile.  It was confused about the address-cells and size-cells values.. It was complaining that the address was not a 64 bit number. (and on the zynqmp I'm sure it puts out 64 bit addresses and works).  So I added the #address-cells = <1>; and #size-cells = <1>; to the dtsi file and it was happy.

It was also complaining about the dma-channel@40400030 {} block having a name but not a reg ?  probably not needed as the driver probably assumes this information anyway.  But I added a reg = <0x40400030 0x20> and that made it happy.

It might be worth filing a bug against whatever generates these patterns for the overlays.  In the normal device-tree I think it would inherit the value from the parent.. but with the overlay I'm not sure how dtc resolves that (or if it even can).

So got it loading and now to see if it actually works :)

 

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Registered: ‎09-12-2007

Re: Warnings with generated with pl.dtsi with dtc 1.5

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Great, thanks for reporting back.

I'll test the zynq 7000 flow when I get some time

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Registered: ‎09-12-2007

Re: Warnings with generated with pl.dtsi with dtc 1.5

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I have attached a patch for the DTG against xilinx-v2018.3 branch that fixes this issue.

I have also updated the helper_proc.tcl to work on the zynq too.

I tested on a zc702 and this work for me.

 

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Registered: ‎09-10-2018

Re: Warnings with generated with pl.dtsi with dtc 1.5

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An interesting follow up.. I hand edited the pl.dtsi file to add the address-cells and size-cells (didn't use the patch).  I posted a snippit of one of the dma sections below.  But now when I try to load in the overlay, it seems to work the first time.. but then if I unload the overlay, and then reload it, it seems to load the FPGA image, but it hangs one of the cores.

Not sure what is going on, but it might be worth checking out before that patch makes it into the mainline..

 

This is a snippit, with just the address-cells and size-cells added to axi_dma_0

 

fragment@2 {
target = <&amba>;
overlay2: __overlay__ {
#address-cells = <1>;
#size-cells = <1>;
axi_dma_0: dma@40400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_s2mm_aclk";
clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>;
compatible = "xlnx,axi-dma-7.1", "xlnx,axi-dma-1.00.a";
interrupt-names = "s2mm_introut";
interrupt-parent = <&intc>;
interrupts = <0 29 4>;
reg = <0x40400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@40400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 29 4>;
xlnx,datawidth = <0x20>;
xlnx,device-id = <0x0>;
};
};

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