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Participant gtushar
Registered: ‎02-08-2016

What does Excluding an Address segment do?

I was working on the Xilinx PYNQ-Z1 board with ZYNQ processor.

I created a simple model where PS is connected to AXI DMA through AXI interconnect .

After connected the block diagram, I got some unconnected slaves which I connected using Auto_assign address .



As soon as I fire the command :

>> dma = overlay.axi_dma_0

everything hangs.


So I searched online and saw an example where someone used Exclude address segment with a different offset. I did the exact same thing and it worked. Following is the new address setting:



I don't understand how this addressing worked in my design.

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2 Replies
Registered: ‎04-20-2017

Re: What does Excluding an Address segment do?

To exclude addresses, so they are not touched by mmu/Linux makes sense esp for dma

Usually Linux is in control of your memory and decides where to put what. Dma in simple operation needs continuous memory (the next address is the previous +1). Linux does not guarantee that tge memory it allocates for smt is continuous (except with some kernel driver which does that)

The easier option is to just exclude some memory from Linux. Your Dma has always the same physical addresses to write to, you can access them with mmap in user's pace and Linux won't fiddle with it.
Only drawback is that the excluded memory can also not be used for smt else by Linux.

So far i was only aware that you can do that by fiddling the device tree not in vivado. But here in this case I assume it's the same result just set at a different place
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Registered: ‎02-07-2008

Re: What does Excluding an Address segment do?

As for your question, when you have multiple masters in a system, and a single AXI Interconnect to connect them to the slaves, by "auto assigning" the addresses, you give all of the masters access to all of the slaves. Typically this is not necessary as some of the masters only need access to specific things, for example, the DMA's MM2S and S2MM interfaces only need access to the DDR via the high-performance slave (HP) port. For this reason we have the "Exclude segment" option, so that we can limit each master's access to only the slave interfaces that it needs to access.


By excluding a slave interface from a master's access, we remove unnecessary master-to-slave paths in the AXI Interconnect thus simplifying the design. This can be a very helpful practice when you have a big AXI Interconnect that's causing you to fail timing closure.


As for your specific issue, if you posted an image of your block diagram I might be able to make some sense of why it's hanging.



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