03-05-2018 05:53 PM
I was working on the Xilinx PYNQ-Z1 board with ZYNQ processor.
I created a simple model where PS is connected to AXI DMA through AXI interconnect .
After connected the block diagram, I got some unconnected slaves which I connected using Auto_assign address .
SEE IMAGE 1
As soon as I fire the command :
>> dma = overlay.axi_dma_0
So I searched online and saw an example where someone used Exclude address segment with a different offset. I did the exact same thing and it worked. Following is the new address setting:
SEE IMAGE 2
I don't understand how this addressing worked in my design.
03-05-2018 10:53 PM
09-04-2018 05:42 AM - edited 09-04-2018 06:44 AM
As for your question, when you have multiple masters in a system, and a single AXI Interconnect to connect them to the slaves, by "auto assigning" the addresses, you give all of the masters access to all of the slaves. Typically this is not necessary as some of the masters only need access to specific things, for example, the DMA's MM2S and S2MM interfaces only need access to the DDR via the high-performance slave (HP) port. For this reason we have the "Exclude segment" option, so that we can limit each master's access to only the slave interfaces that it needs to access.
By excluding a slave interface from a master's access, we remove unnecessary master-to-slave paths in the AXI Interconnect thus simplifying the design. This can be a very helpful practice when you have a big AXI Interconnect that's causing you to fail timing closure.
As for your specific issue, if you posted an image of your block diagram I might be able to make some sense of why it's hanging.