08-28-2020 09:47 AM
I am new to the ZYNQ SOC system and embedded Linux, in the process of learning the basics. I built a test system to read an external voltage with the XADC vpvn channel and streaming using DMA transfers.
Main features of the system are:
I use a pynq-z1 board for this test. (only board I have)
In my design there is a FIFO after the XADC and the a custom IP (tlast_generator) to add the TLAST signal 9and also to latch (it also latches the FIFO_full status bit for monitoring).
A GPIO IP is used to control and monitor status of the system (ie. to set the packet size, monitor if FIFO full flag ... etc).
DMA data width is 4 bytes, lower 2 bytes are the XADC value, and upper two bytes are a counter value I add in the tlast_generator, (just for debugging).
It works fine in the bare metal mode and reads voltages and streams data correctly. Then I tried it in linux. I use petalinux 19.2 to build the linux system and use a custom device driver i wrote to control the DMA.
When it is tested, DMA seems to works fine, but the streamed XADC values looks rather strange. First DMA transfer is all zeros, subsequent transfers show values that that looks rater random and not what I expect from the XADC.
As a cross check I replaced the XADC with a sample generator (a 16 bit counter). In that case first transfer is still zeros, but subsequent transfer values looks correct. So I guess at least one of the issues I have is with the XADC. I configure XADC in vivado, and leave unchanged after that.
Is there any XADC installations I have to do in linux? or is there anything I have missed. Since it works in bare metal I assume the design is fine and the problem is in linux side. Any help to resolve this is greatly appreciated. Already I spent several days to figure out what is wrong, without any success . I attach the layout of the design, my DMA kernel driver and the user level test application code.
08-29-2020 11:05 AM
I was able to solve it by disabling the default Xilinx XADC driver in the kernel configuration menu. (by default it is enabled).
IIO drivers > ADC drivers > Xilinx XADC Driver
This looks somewhat counter intuitive to me, but it works! (after almost a week of hacking).
Still the very first DMA transfer is all zeros, I can live with that but would like to understand what causing it.