XADC module

[pedro4]

(Not sure if this thread should go in "Zynq All Programmable SoC". If so, please feel free to move it)

Hello everyone. I'm having quite a hard time trying to make these two (XADC and Xillybus/Xillinux) work together and I was hoping someone here could lend me a hand.

Basically, what I am trying to achieve is: I'll input some analog signals to VP/VN, Vaux0 and Vaux8 to the XADC. I want it to convert them and that conversion to be written to a FIFO that can be read by Xillybus, which will make it available for me in Xillinux (so with a simple command I can dump the conversion into a file). A more visual way to explain this would be:

Problem: I am getting nothing but zeros from Xillybus. How am I collecting this data? Xillinux comes with a few demo apps. I've modified one of them (streamread.c) so I can write whatever is reading to a file. So I connect to Xillinux via SSH and run this:

touch output
./streamread /dev/xillybus_datastream output

This output keeps getting bigger as long as streamread is running but as I said, there's nothing but 0000000...

Info: I generated the XADC using the wizard so I guess everything is properly instantiated.

Tests I've run so far:

• I've tried the XADC and Xillybus separately and they both work just fine. For the XADC, I followed this tutoral here and I managed to get readings from all inputs (and even temperature!) in spite of the fact that I wasn't even feeding it (all it was reading was noise). As for Xillybus, I tried a loopback FIFO where I could write something in the terminal and see it in a different one, so that worked good as well.
• Since XADC outputs 16-bit data, I had to create a new Xillybus project (I made it using the IP Core generator they have built in their website) to add a 16-bit-wide FIFO (actually, they had to be 2 since one is from host to FPGA and the other one from FPGA to host, although I'm only interested in the latter). I updated Xillybus accordingly and tested it by creating a simple VHDL that would send some characters to the FIFO if switch 1 was high. Worked like charm. I even used ./streamread /dev/xillybus_datastream output to make sure streamread was working properly and it was.
• This one I can't understand why is happening, but it's happening. I modified my VHDL code and used 4 LEDs of the Zedboard to see if the XADC was working good. So I took the last 4 bits of the conversion of the XADC and associated them with one LED each (LED0 with dout(0), LED1 with dout(1), and so on). They never turned on so the XADC was outputting zeros or it wasn't working at all. So I decided to do this: DRDY signal from XADC = LED1 and EMPTY flag from FIFO = LED2. LED1 was turned off the whole time (XADC wasn't converting) but to my surprise, EMPTY flag was always 1. I mean, that makes sense, if DRDY is never 1, it can't write to the FIFO (cause that DRDY acts as the wr_en for the FIFO) but then how am I getting so many zeros in Xillinux when using streamread? Isn't Xillybus supposed to not read from the FIFO if the EMPTY flag is high?

I don't know what else to try, really. Hope you can guide me through this. If you need any more info like source code or something, I will gladly share it.

Thank you (and sorry for the long post )

[austin]

p,

Are you following

https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0ahUKEwiMwIOcvYnVAhWGa1AKHUxkDjgQFggwMAE&url=https%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fuser_guides%2Fug480_7Series_XADC.pdf&usg=AFQjCNFhLVU_-Ffd6rQOrNEGRvlalyX91g

?

[billauer]

Hello,

I'll start with the third bullet: If nothing is written to the FIFO going to the Xillybus IP core, there should indeed be no data for reading (the read() call blocks until data arrives). When you say that LED1 was turned off all the time, was that measured with a trigger of a digital scope, or with the naked eye? If it's the latter, a LED that appears off may actually turn on for a few nanoseconds every now and then, without the human eye noticing.

As for your way to capture data, I would just go

cat /dev/xillybus_datastream > output.dat

or for an immediate response

hexdump -C /dev/xillybus_datastream

And now to the point. It's difficult to speculate without seeing the VHDL code that connects the XADC to the FIFO, but I can try two wild guesses. The first one is that something is wrong with the connection between the XADC and the FIFO (data wire disconnected, or the XADC runs on a different clock from the side of the FIFO that accepts the data). The second thing I would look at is if the clock that the XADC runs on is within the allowed range (i.e. if ADCCLK's frequency is OK). Just a couple of shots in the dark.

Regards,

   Eli

[pedro4]

@austin yes, I've been following that since the very beginning, thank you.


@billauer Hi, thanks for your reply. About LED1, I have limited access to my university lab equipment so I ran most of the tests at home. I used my eyes to test that and you're right about that, I might have missed the LED going on for a few nanoseconds. But then I decided to make a simple finite-state machine that has drdy as input signal and it will output 1 if drdy ever goes high, that way I will be able to see it. So I did that and the LED never turned on so I think I can confirm drdy is never 1. Plus I also tried with busy signal from XADC and it's always 1 (again with the LEDs)

About capturing data, I tried cat /dev/xillybus_datastream > output.dat and it says device or resource busy not sure if that means something? As for hexdump -C /dev/xillybus_datastream I many zeros as I was getting the way I was doing it.

I have both the XADC and the FIFO fed with the same clock and that's the one from Xillybus. It's a 100 MHz clock and the XADC was set up in the wizard with a DCLK frequency of 100 MHz and 1 MSPS. Below that two text boxes there is a text in the wizard that says ADC CLK 25 MHz (that is DCLK/4) so I suppose that is right too.

I have checked a hundred times connections between the XADC and the FIFO and I see nothing wrong, but who knows... I'll attatch my project in case you want take a look and maybe find something I'm ignoring. I commented the lines where I use the LEDs and left it as I'd run my project normally. In case you want to use then just uncomment the proper lines. Also, if you want to test it on a real zedboard you'd need to mount the image in an SD card, the .bit is already inside the zip (all the code is inside xillybus_xadc\vhdl\vivado. I'm using Vivado 2016.4 btw)

Had to upload it to MEGA since I was exceeding the allowed limit size: https://mega.nz/#!JahnDSZC!HXAAVYbnJb0k8_UB6QtA7IKrvPJiIepsFEGad5HBI-s

Thank you!

[billauer]

First, regarding the "device or source busy". I can mean a lot of things, but odds are that you happened to have some other process running with the device file open.

As for your issue with the XADC. I say, when everything else fails, read the warnings. ;)

From your synthesis report:

WARNING: [Synth 8-614] signal 'c_MEASURED_VPVN' is read in the process but is not in the sensitivity list [D:/WorkspaceVHDL/xillybus_xadc/vhdl/vivado/xillydemo.srcs/sources_1/new/top_xadc.vhd:123]
WARNING: [Synth 8-614] signal 'c_MEASURED_VAUX0' is read in the process but is not in the sensitivity list [D:/WorkspaceVHDL/xillybus_xadc/vhdl/vivado/xillydemo.srcs/sources_1/new/top_xadc.vhd:123]
WARNING: [Synth 8-614] signal 'c_MEASURED_VAUX8' is read in the process but is not in the sensitivity list [D:/WorkspaceVHDL/xillybus_xadc/vhdl/vivado/xillydemo.srcs/sources_1/new/top_xadc.vhd:123]
WARNING: [Synth 8-614] signal 'do' is read in the process but is not in the sensitivity list [D:/WorkspaceVHDL/xillybus_xadc/vhdl/vivado/xillydemo.srcs/sources_1/new/top_xadc.vhd:123]

I would add these signals to the sensitivity list and see if that helps...

Regards,

   Eli

[pedro4]

@billauer I missed that! I did a testbench for the xadc (tb_top_xadc.vhd) and everything worked fine so I didn't even see those warnings. Anyway, I've added them to the sensitivity list but still got same result... I also got these warnings:

• [Project 1-486] Could not resolve non-primitive black box cell 'fifo_16x512' instantiated as 'my_system/fifo_datastream/fifo' ["D:/WorkspaceVHDL/xillybus_xadc/vhdl/vivado/xillydemo.srcs/sources_1/new/fifo.vhd":62]
• [Project 1-486] Could not resolve non-primitive black box cell 'xadc_wiz_0' instantiated as 'my_system/xadc/xadc' ["D:/WorkspaceVHDL/xillybus_xadc/vhdl/vivado/xillydemo.srcs/sources_1/new/top_xadc.vhd":99]
• [Project 1-486] Could not resolve non-primitive black box cell 'xillybus_core' instantiated as 'xillybus_ins/xillybus_core_ins' ["D:/WorkspaceVHDL/xillybus_xadc/vhdl/src/xillybus.v":286]
• [Project 1-486] Could not resolve non-primitive black box cell 'xillybus_lite' instantiated as 'xillybus_ins/system_i/vivado_system_i/xillybus_lite_0/U0' ["d:/WorkspaceVHDL/xillybus_xadc/vivado-essentials/vivado_system/ip/vivado_system_xillybus_lite_0_0/synth/vivado_system_xillybus_lite_0_0.vhd":156]
• [Project 1-486] Could not resolve non-primitive black box cell 'xillyvga_core' instantiated as 'xillybus_ins/system_i/vivado_system_i/xillyvga_0/inst/xillyvga_core_ins' ["d:/WorkspaceVHDL/xillybus_xadc/vivado-essentials/vivado_system/ipshared/33bf/xillyvga.srcs/sources_1/imports/verilog/xillyvga.v":64]

But I don't think this is an actual problem, since I can access the FIFO and already tested via LEDs the XADC "is" there.

Did you see anything wrong with connections or the CLK?

[billauer]

Hi,

Those warnings are normal.

Regards,

   Eli

[pedro4]

@billauer Could it be there is bug in Xillybus that won't allow me to use it with XADC? I don't know what to think anymore, I've tried everything, maybe it's because of that that isn't working?

[billauer]

Hello,

Given that Xillybus is being used by hundreds of engineers and researches worldwide in various fields and usage scenarios, without a single functional issue for several years, I wouldn't consider Xillybus the immediate suspect.

I suggest generating some dummy data with just some logic to see that you've got that part figured out.

Regards,

   Eli

[pedro4]

@billauer Do you mean that I should replace the XADC with something that will write to the FIFO and see if Xillybus is getting that right? If that's what you mean, I already did that. I made a VHDL code that would send 6 bytes to the FIFO as long as Switch1 was enabled and worked fine. If you didn't mean that, could you please elaborate? Thanks!

[billauer]

Indeed, that's what I meant.

At this stage, what people usually do is to fish out some information on what's going on with the XADC module and why it doesn't work as you'd expect. Sometimes Xillybus is useful to transport debug information (in particular when there's a lot of data to move), but in your case it seems like you'll need to look at waveforms.

So I would hook up some signals with Chipscope and see if things happen there as I expect.

Regards,

   Eli