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prem
Visitor
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Registered: ‎03-29-2021

XEN AXI DMA (PL Master) information required for zcu102

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Hello Everyone,
I am a new to XEN and the MPSoC, i hope this is the right forum for this post.

I am using the latest version of the zcu102 development board and i am trying to create a barematal application that uses the AXI DMA on the PL. I have followed the tutorial from simple AXI DMA in vivado , AXI DMA in youtube and use the AXI DMA SG polling example in SG Polling example . This works perfectly fine in baremetal, i was able to verify this in vivado using ILA as well.

dma_vivado.png

 

Now i want to make this as a baremetal hypervisor guest, in future this will be replaced by a custom IP.

I followed this tutorial Baremetal DomU guest changed the base address to 0x4000000,(1GB allocated to Dom-0) to create my EL1 binary. I used Petalinux 2020.2 to generate my linux, xen image and use tftp to boot. When i run start the guest i manually added printf for debug, the execution stops at XAxiDma_BdRingCreate(TxRingPtr, TX_BD_SPACE_BASE,TX_BD_SPACE_BASE,XAXIDMA_BD_MINIMUM_ALIGNMENT, BdCount);

function prototype XAxiDma_BdRingCreate(XAxiDma_BdRing * RingPtr, UINTPTR PhysAddr,UINTPTR VirtAddr, u32 Alignment, int BdCount);

Here both the physical address and virtual address are the same. I am completely lost at this point, i am not sure what should be tweaked to make this work. I would really appreciate if someone help me understand what needs to be changed in the software, device tree+passthrough and also in vivado if i need to manually assign AXI ID's?

From what i understand from the xilinx tutorials Xen+and+PL+Masters section 3 and MPSOC SMMU section 4, stream ids are required by the SMMU to get the correct address translation.

Since i use the S_AXI_HP0_FPD i tried manually setting the the stream id of 0x280 (obtained from TRM chapter 16) with AXI id bits set to 0 in the xen.dtsi, i got the following output when xen boots

stream_id.png

 

I have also tried leaving the dtdev line empty as suggested in the tutorial, didn't work, may be i made a mistake somewhere!

Going through the checklist in the Xen+and+PL+Masters i still could not understand how to get the stream id and set the dtdev in the guest config file.

I would really appreciate if someone can help me with the following questions

  1. Do i have to set AxPROT to 0x2 in vivado?
  2. Do i need a AXI side band formatter IP (PG 307document) to set the stream ID?
  3. What changes need to be added to the xen.dtsi?
  4. or what needs to be changed in the software?

Xen Guest .cfg used to start the AXI transactions

#Guest name
  name = "dma"
# Kernel image to boot
  kernel = "/bin/xaxidma_example_sg_poll_2.bin"
# Kernel command line options - Allocate 8MB
  memory = 8
# Number of VCPUS
  vcpus = 1
# Pin to CPU 0
  cpus = [1]
# uart1 irq
  irqs = [ 54 ]
#uart1 and axilite config
  iomem = [ "0xff010,1","0xa0000,1"]

xen.dtsi is where i made my custom changes

&smmu {
	status = "okay";
	mmu-masters = < &gem0 0x874
			&gem1 0x875
			&gem2 0x876
			&gem3 0x877
			&dwc3_0 0x860
			&dwc3_1 0x861
			&qspi 0x873
			&lpd_dma_chan1 0x868
			&lpd_dma_chan2 0x869
			&lpd_dma_chan3 0x86a
			&lpd_dma_chan4 0x86b
			&lpd_dma_chan5 0x86c
			&lpd_dma_chan6 0x86d
			&lpd_dma_chan7 0x86e
			&lpd_dma_chan8 0x86f
			&fpd_dma_chan1 0x14e8
			&fpd_dma_chan2 0x14e9
			&fpd_dma_chan3 0x14ea
			&fpd_dma_chan4 0x14eb
			&fpd_dma_chan5 0x14ec
			&fpd_dma_chan6 0x14ed
			&fpd_dma_chan7 0x14ee
			&fpd_dma_chan8 0x14ef
			&sdhci0 0x870
			&sdhci1 0x871
			&nand0 0x872>;
};

&uart1{
	xen,passthrough = <0x1>;
};

 

Generated pl.dtsi

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version:  
 * Today is: Thu Apr 22 16:23:31 2021
 */


/ {
	amba_pl: amba_pl@0 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges ;
		axi_dma_0: dma@a0000000 {
			#dma-cells = <1>;
			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
			clocks = <&zynqmp_clk 71>, <&zynqmp_clk 71>, <&zynqmp_clk 71>, <&zynqmp_clk 71>;
			compatible = "xlnx,axi-dma-7.1", "xlnx,axi-dma-1.00.a";
			interrupt-names = "mm2s_introut", "s2mm_introut";
			interrupt-parent = <&gic>;
			interrupts = <0 89 4 0 90 4>;
			reg = <0x0 0xa0000000 0x0 0x10000>;
			xlnx,addrwidth = <0x20>;
			xlnx,include-sg ;
			xlnx,sg-length-width = <0xe>;
			dma-channel@a0000000 {
				compatible = "xlnx,axi-dma-mm2s-channel";
				dma-channels = <0x1>;
				interrupts = <0 89 4>;
				xlnx,datawidth = <0x20>;
				xlnx,device-id = <0x0>;
			};
			dma-channel@a0000030 {
				compatible = "xlnx,axi-dma-s2mm-channel";
				dma-channels = <0x1>;
				interrupts = <0 90 4>;
				xlnx,datawidth = <0x20>;
				xlnx,device-id = <0x0>;
			};
		};
	};
};

My linux boot log is also attached for reference. I have tried looking at looking at some of the forum answers, they are quite old and does not help me completely.

https://forums.xilinx.com/t5/Embedded-Linux/Xen-does-not-support-more-than-one-PL-to-PS-interrupt-for-axi/m-p/924816  

https://forums.xilinx.com/t5/Embedded-Linux/Baremetal-DomU-application-with-AXI-DMA-passthrough-Xen/td-p/925742  

https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Basic-SMMU-Questions-with-Custom-IP/m-p/860907#M40597  


I look forward for your answers.

Thanks and Best Regards,

Prem

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prem
Visitor
Visitor
267 Views
Registered: ‎03-29-2021

Hi Deanna,

Thank you very much for your reply and helping me understand the stream ID formation and with the AxPROT bits. I also had help from the xen forums, special thanks to Stefano for explaining the xen configuration.

I was finally able run the DMA from PL as a XEN Guest, with some changes.

  1. I disabled the SG mode to make it simple and set the AxPROT bits to 0x2 in Vivado
  2. The stream id is 0xE80 and it is set in xen.dtsi
  3. Changes made in petalinux for xen config is attached in xen.dtsi and the guest config files are also attached for both polling and interrupt modes
  4. I used the source code from Xilinx Github  and had to change only the base address to 0x40000000 in c and linker script
  5. (Optional) the memory allocation is 256MB for the guest and can be reduced after altering the offset in the C code to a suitable base address.

Hope this is useful for others those who want to recreate the design.

Best Regards,

Prem

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2 Replies
demarco
Xilinx Employee
Xilinx Employee
392 Views
Registered: ‎10-04-2016

Hi @prem ,

I'm far from a Xen expert, but I can help with some of the AXI details.

Your Stream ID isn't formed properly. The Stream ID is a 15-bit values with bits [14:10] coming from the TBU number that the port passes through and bits [9:0] coming from the Master ID list in Table 16-13 in UG1085. For HP0 the TBU number is 0x3 and the port master ID is 1010, AXI ID[5:0] from the PL. Vivado will tie off the AXI ID bits to 6'h00. Put all of that together and the Stream ID should be 0xE80.

The way I interpret section 6.5 of the Wiki, you need to tie off the AxPROT bits to 3'b010 so that the AXI DMA generates non-secure transactions.

You don't need the AXI Sideband Formatter. This IP is helpful if you have multiple masters trying to use HP0 and want to give them different access permissions. The AXI Sideband Formatter allows you to control the setting of the AXI ID[5:0] bits to distinguish between masters. It would be unusual to need this for a single AXI DMA.

Regards,

Deanna

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prem
Visitor
Visitor
268 Views
Registered: ‎03-29-2021

Hi Deanna,

Thank you very much for your reply and helping me understand the stream ID formation and with the AxPROT bits. I also had help from the xen forums, special thanks to Stefano for explaining the xen configuration.

I was finally able run the DMA from PL as a XEN Guest, with some changes.

  1. I disabled the SG mode to make it simple and set the AxPROT bits to 0x2 in Vivado
  2. The stream id is 0xE80 and it is set in xen.dtsi
  3. Changes made in petalinux for xen config is attached in xen.dtsi and the guest config files are also attached for both polling and interrupt modes
  4. I used the source code from Xilinx Github  and had to change only the base address to 0x40000000 in c and linker script
  5. (Optional) the memory allocation is 256MB for the guest and can be reduced after altering the offset in the C code to a suitable base address.

Hope this is useful for others those who want to recreate the design.

Best Regards,

Prem

View solution in original post