UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
2,163 Views
Registered: ‎06-22-2017

Xilinx Emaclite Time Stamping - PTP4L

I am using the Xilinx Emaclite driver for an ethernet port connected through FMC. This FMC Ethernet modules has a DP83640 PHY, which supports Hardware phy level time stamping. I added the following lines to the emaclite driver in order to execute the ptp4l:

static int xemaclite_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
{
        if (!netif_running(ndev))
                return -EINVAL;
        if (!ndev->phydev)
                return -EINVAL;
        return phy_mii_ioctl(ndev->phydev, rq, cmd);
}

 

However, when I execute ptp4l I get the following error:

ptp4l[1138.006]: timed out while polling for tx timestamp
ptp4l[1138.006]: increasing tx_timestamp_timeout may correct this issue, but it is likely caused by a driver bug
ptp4l[1138.006]: port 1: send sync failed
ptp4l[1138.006]: port 1: MASTER to FAULTY on FAULT_DETECTED (FT_UNSPECIFIED)

 

It fails in the poll() and I do not know why. Do I need to modify more the emaclite driver?

 

 

0 Kudos