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Registered: ‎04-09-2020

Xilinx dma driver ERR_IrqEN default value

Hello,

I have a project to transfer data by DMA from PS to PL. I'm using a linux driver.
This works fine, I can transfer data. But I have a problem with the register MM2S_DMACR. The interrupt (bit 12) is disable by default, so the mm2s_introut never up. Why Xilinx dma driver disables interrupts just at boot time?

This is my set-up:

- Ultrazed EG (XCZU3EG).
- Vivado 2018.2
- Petalinux 2018.2

If I set the ERR_IrqEN manually (devmem) it runs.

 

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version:  
 * Today is: Wed Apr  8 15:01:34 2020
 */


/ {
	amba_pl: amba_pl@0 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges ;
		axi_bram_ctrl_0: axi_bram_ctrl@80001000 {
			compatible = "xlnx,axi-bram-ctrl-4.0";
			reg = <0x0 0x80001000 0x0 0x1000>;
			xlnx,bram-addr-width = <0xa>;
			xlnx,bram-inst-mode = "EXTERNAL";
			xlnx,ecc = <0x0>;
			xlnx,ecc-onoff-reset-value = <0x0>;
			xlnx,ecc-type = <0x0>;
			xlnx,fault-inject = <0x0>;
			xlnx,memory-depth = <0x400>;
			xlnx,s-axi-ctrl-addr-width = <0x20>;
			xlnx,s-axi-ctrl-data-width = <0x20>;
			xlnx,s-axi-id-width = <0x1>;
			xlnx,s-axi-supports-narrow-burst = <0x0>;
			xlnx,select-xpm = <0x1>;
			xlnx,single-port-bram = <0x1>;
		};
		axi_dma_0: dma@80000000 {
			#dma-cells = <1>;
			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk";
			clocks = <&clk 71>, <&clk 71>, <&clk 71>;
			compatible = "xlnx,axi-dma-1.00.a";
			interrupt-names = "mm2s_introut";
			interrupt-parent = <&gic>;
			interrupts = <0 89 4>;
			reg = <0x0 0x80000000 0x0 0x1000>;
			xlnx,addrwidth = <0x20>;
			xlnx,include-sg ;
			xlnx,sg-length-width = <0x17>;
			dma-channel@80000000 {
				compatible = "xlnx,axi-dma-mm2s-channel";
				dma-channels = <0x1>;
				interrupts = <0 89 4>;
				xlnx,datawidth = <0x20>;
				xlnx,device-id = <0x0>;
				xlnx,include-dre ;
			};
		};
		axi_gpio_0: gpio@80002000 {
			#gpio-cells = <3>;
			clock-names = "s_axi_aclk";
			clocks = <&clk 71>;
			compatible = "xlnx,xps-gpio-1.00.a";
			gpio-controller ;
			reg = <0x0 0x80002000 0x0 0x1000>;
			xlnx,all-inputs = <0x0>;
			xlnx,all-inputs-2 = <0x0>;
			xlnx,all-outputs = <0x1>;
			xlnx,all-outputs-2 = <0x0>;
			xlnx,dout-default = <0x000000AA>;
			xlnx,dout-default-2 = <0x00000000>;
			xlnx,gpio-width = <0x8>;
			xlnx,gpio2-width = <0x20>;
			xlnx,interrupt-present = <0x0>;
			xlnx,is-dual = <0x0>;
			xlnx,tri-default = <0xFFFFFFFF>;
			xlnx,tri-default-2 = <0xFFFFFFFF>;
		};
		axi_stream_multiplex_0: axi_stream_multiplexer_top@90000000 {
			compatible = "xlnx,axi-stream-multiplexer-top-1.0";
			reg = <0x0 0x90000000 0x0 0x1000>;
		};
		psu_ctrl_ipi: PERIPHERAL@ff380000 {
			compatible = "xlnx,PERIPHERAL-1.0";
			reg = <0x0 0xff380000 0x0 0x80000>;
		};
		psu_message_buffers: PERIPHERAL@ff990000 {
			compatible = "xlnx,PERIPHERAL-1.0";
			reg = <0x0 0xff990000 0x0 0x10000>;
		};
	};
};

address_editor.pngblock_diagram.pngdma_ip.png

 

Tags (3)
block_diagram.png
address_editor.png
dma_ip.png
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Registered: ‎04-09-2020

The transaction starts and I can see data transfer in the ILA but driver is not able to finish the transaction (waits indefinitely) because AXI DMA doesn't generate an mm2s_introut interrupt. It doesn't generate it because interrupts are disabled in the AXI DMA MM2S control register.
I can enable them manually. But, why are they disabled by default? Is the devicetree wrong? Or I do need to do something specific in petalinux?

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