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Registered: ‎03-12-2019

ZCU102 Eval with Petalinux: Error using fpgautil (zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13)

Hello all,

I'm in the process of testing loading the bitstream and dtbo through Linux on the ZCU102 eval board.

Setup:

Linux Image built with Yocto

version: rel-v2018.3

IMAGE_FEATURES += " fpga-manager"

HDF file downloaded from https://github.com/Xilinx/hdf-examples/tree/rel-v2018.3/zcu102-zynqmp

defconfig (basically adding the necessary configurations based on https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841847/Solution+ZynqMP+PL+Programming)

Issues:

The issue that I'm having right now is regarding loading the bitstream and dtbo using fpgautil. I got the following messages:

[ 525.860739] fpga_manager fpga0: writing design_1_wrapper.bit.bin to Xilinx ZynqMP FPGA Manager
[ 526.081843] zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13
Time taken to load DTBO is 232.000000 Milli Seconds
DTBO loaded through zynqMP FPGA manager successfully

The error seems to be indicating that there's some access permission issue as I was trying to hunt down the issue.

Now this is where I'm getting stuck.

I'm not sure on how to proceed or where to check next. Any info would be greatly appreciated.

The error seems to be just a warning from reading the code. I would like to understand where the problem is coming from and whether it is serious or not.

Thanks,

Nam

 

 

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370 Views
Registered: ‎02-07-2018

Re: ZCU102 Eval with Petalinux: Error using fpgautil (zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13)

Hi nanguyen@drw.com 

 

Please refer this below links for loading the bitfile to FPGA from u-boot & Linux.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842056/FPGA+Manager+ZCU102

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841847/Solution+ZynqMP+PL+Programming#SolutionZynqMPPLProgramming-FPGAprogrammingusingsysfsattributes

 

Thanks & regards

Aarivnd

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Registered: ‎03-12-2019

Re: ZCU102 Eval with Petalinux: Error using fpgautil (zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13)

@aravindb 

Hi Aravind,

Thank you for your response.

In my original post, in the setup section, I have already followed the 2nd link you sent. I'm interested in loading the bitstream through Linux.

Now, why I'm posting is because even though following the same instruction, I'm getting the error zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13.

The error seems to becoming from when making a call to the firmware (in firmware.c). But that's where I'm not sure what to look for next and hence asking for some guidance.

Thanks,

Nam

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