Hi, I'm experimenting the Xen hypervisor on ZCU106. I am currently using Petalinux 2019.1, Vivado 2019.1 and SDx 2019.1
I am currently having issues with running matrix multiplication accelerator example synthesized with SDx and having Xen enabled at the same time. I am currently following this guide to launch Xen with Petalinux since the guide from the Xilinx Wiki didn't seem to work. For the PL side, I am not very familiar with synthesis and creating application with Vivado and SDK, so I chose to go with the SDx instead. I followed chapter 3 of UG1146 exactly to generate the hardware platform but followed "Linux Boot Files" section of the same guide to generate Petalinux. While configuring Petalinux, I modified it to have Xen-related settings enabled (Changing the packaging configuration to INITRD, adding Xen on filesystem configuration, modifying the device tree to include xen.dtsi). I also modified Petalinux as mentioned in "Linux Boot Files" section of UG1146 (Changing Size in megabytes, adding staging drivers, turning off CPU power management, adding stdc++ llibs, modifying device tree to include xlnk) and added GDB just in case to debug what was going on the board. Then I synthesized the matrix multiplication example from SDx using the created platform, set up the SD card as mentioned in the Xen guide and booted the board. I was able to boot into Dom0 of Xen, but wasn't able to run the compiled elf file generated by SDx. It just displays "Killed" and seems to generate segmentation fault from the libc and never reach main when it was debugged using GDB from the board. I thought that the device tree configuration was the problem and found this guide from Xilinx wiki on how to set the device tree to enable PL logic. It seems that all configurations that the guide is mentioning is already done on xen.dtsi. I saw some forum posts asking about passthroughs to DomU and if that is possible, I think that accessing the PL logic from Dom0 is also possible.
My questions are:
1. Is it actually possible to execute tasks involving PL on Dom0? If so, is it possible to synthesize such design and compile the binary file using SDx?
2. How can I configure the SDx platform hardware / software to enable PL logic communication from Dom0 of Xen?
3. Can adding AXI sideband formatter IP solve this issue? If so, how can I integrate this IP to the SDx platform hardware?