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Participant werr4ever
Participant
200 Views
Registered: ‎09-24-2018

ZCU111: PL DRAM read-Bare Metal

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I have a very simple design where the Ultrascale+ processor reads and write to the DDR4 on the PL Side (MT40A512M16JY-075E).  The design is attached.  In short, it is basically a HPM-FPD AXI MM interface from the Ultrascale+ which inputs to a axi smart connect core, then to the DDR4 Controller (MIG).  Programming the Device using the Hardware Manager, I saw the MIG CAL test passing, which led me to believe I successfully connected the pin in and out correctly for the PL side DDR4. 

The address editor in Vivado pointed out the ddr4 is on address 0x400000000 (See attached) to 0x4FFFFFFFF.  On Xilinx SDK, I wrote an application code that does the following:

uint32_t* ptr = 0x400000000;

uint32_t test = ptr[0];

Running this section of code eventually hangs up the processor.  On the SystemILA side, the processor doesn't seem like it is reading anything from the HPM-FPD AXI MM bus.  Is there something I am misconfiguring on the system that is not allowing the Ultrascale+ to read from the PL-Side DDR4 memory.

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ZCU111_DDR4.PNG
DDR4_ADDRESS.PNG
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Participant werr4ever
Participant
99 Views
Registered: ‎09-24-2018

Re: ZCU111: PL DRAM read-Bare Metal

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This is resolved needed a FSBL and a PMU firmware to get this to work.

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Participant werr4ever
Participant
100 Views
Registered: ‎09-24-2018

Re: ZCU111: PL DRAM read-Bare Metal

Jump to solution

This is resolved needed a FSBL and a PMU firmware to get this to work.

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