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Registered: ‎08-09-2018

ZYNQ 7000 hangs on boot after adding uartlite

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Hello,

 

I am experiencing an error on startup where Linux hangs during the boot process after I added a uartlite block to the FPGA. I am using Vivado 2018.1 and Linux kernel 4.14 on a ZYNQ 7000.

I found a workaround to boot the kernel by commenting out the following lines in the uartlite.c driver in the kernel in the ulite_assign function. Of course the uart does not work properly in this case.

I have enabled the uartlite in the Kernel Config when building as stated in the wiki http://www.wiki.xilinx.com/Uartlite+Driver

	/*
		spin_lock_init(&port->lock);
		port->fifosize = 16;
		port->regshift = 2;
		port->iotype = UPIO_MEM;
		port->iobase = 1; // mark port in use
		port->mapbase = base;
		port->membase = NULL;
		port->ops = &ulite_ops;
		port->irq = irq;
		port->flags = UPF_BOOT_AUTOCONF;
		port->dev = dev;
		port->type = PORT_UNKNOWN;
		port->line = id;
		port->private_data = pdata;
*/

I am also including here my devicetree and console output on an unsuccessful boot attempt.

 

Any help with this would be greatly appreciated as I have been trying to get this to work for several days now.

 

Regards,

Paul

 

/dts-v1/;

/ {
	#address-cells = <0x1>;
	#size-cells = <0x1>;
	model = "cellXica SC6 Platform";
	compatible = "xlnx,zynq-sc6", "xlnx,zynq-7000";

	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x0>;
			clocks = <0x1 0x3>;
			clock-latency = <0x3e8>;
			cpu0-supply = <0x2>;
			operating-points = <0xb71b0 0xf4240 0x5b8d8 0xf4240>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x1>;
			clocks = <0x1 0x3>;
		};
	};

	fpga_full: fpga-full {
		compatible = "fpga-region";
		fpga-mgr = <0x3>;
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges;
	};

	pmu@f8891000 {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
		interrupt-parent = <0x4>;
		reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
	};

	regulator_vccpint: fixedregulator {
		compatible = "regulator-fixed";
		regulator-name = "VCCPINT";
		regulator-min-microvolt = <0xf4240>;
		regulator-max-microvolt = <0xf4240>;
		regulator-boot-on;
		regulator-always-on;
		linux,phandle = <0x2>;
		phandle = <0x2>;
	};

	amba: amba {
		u-boot,dm-pre-reloc;
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		interrupt-parent = <0x4>;
		ranges;

		adc: adc@f8007100 {
			compatible = "xlnx,zynq-xadc-1.00.a";
			reg = <0xf8007100 0x20>;
			interrupts = <0x0 0x7 0x4>;
			interrupt-parent = <0x4>;
			clocks = <0x1 0xc>;
		};

		can0: can@e0008000 {
			compatible = "xlnx,zynq-can-1.0";
			status = "disabled";
			clocks = <0x1 0x13 0x1 0x24>;
			clock-names = "can_clk", "pclk";
			reg = <0xe0008000 0x1000>;
			interrupts = <0x0 0x1c 0x4>;
			interrupt-parent = <0x4>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
		};

		can1: can@e0009000 {
			compatible = "xlnx,zynq-can-1.0";
			status = "disabled";
			clocks = <0x1 0x14 0x1 0x25>;
			clock-names = "can_clk", "pclk";
			reg = <0xe0009000 0x1000>;
			interrupts = <0x0 0x33 0x4>;
			interrupt-parent = <0x4>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
		};

		gpio0: gpio@e000a000 {
			compatible = "xlnx,zynq-gpio-1.0";
			#gpio-cells = <0x2>;
			clocks = <0x1 0x2a>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x14 0x4>;
			reg = <0xe000a000 0x1000>;
			emio-gpio-width = <0x40>;
			gpio-mask-high = <0x0>;
			gpio-mask-low = <0x5600>;
			linux,phandle = <0x5>;
			phandle = <0x5>;
		};

		i2c0: i2c@e0004000 {
			compatible = "cdns,i2c-r1p10";
			status = "disabled";
			clocks = <0x1 0x26>;
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x19 0x4>;
			reg = <0xe0004000 0x1000>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};

		i2c1: i2c@e0005000 {
			compatible = "cdns,i2c-r1p10";
			status = "disabled";
			clocks = <0x1 0x27>;
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x30 0x4>;
			reg = <0xe0005000 0x1000>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};

		intc: interrupt-controller@f8f01000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <0x3>;
			interrupt-controller;
			reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
			num_cpus = <0x2>;
			num_interrupts = <0x60>;
			linux,phandle = <0x4>;
			phandle = <0x4>;
		};

		L2: cache-controller@f8f02000 {
			compatible = "arm,pl310-cache";
			reg = <0xf8f02000 0x1000>;
			interrupts = <0x0 0x2 0x4>;
			arm,data-latency = <0x3 0x2 0x2>;
			arm,tag-latency = <0x2 0x2 0x2>;
			cache-unified;
			cache-level = <0x2>;
		};

		mc: memory-controller@f8006000 {
			compatible = "xlnx,zynq-ddrc-a05";
			reg = <0xf8006000 0x1000>;
		};

		ocmc: ocmc@f800c000 {
			compatible = "xlnx,zynq-ocmc-1.0";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x3 0x4>;
			reg = <0xf800c000 0x1000>;
		};

		uart0: serial@e0000000 {
			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
			status = "okay";
			clocks = <0x1 0x17 0x1 0x28>;
			clock-names = "uart_clk", "pclk";
			reg = <0xe0000000 0x1000>;
			interrupts = <0x0 0x1b 0x4>;
			device_type = "serial";
			port-number = <0x1>;
		};

		uart1: serial@e0001000 {
			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
			status = "okay";
			clocks = <0x1 0x18 0x1 0x29>;
			clock-names = "uart_clk", "pclk";
			reg = <0xe0001000 0x1000>;
			interrupts = <0x0 0x32 0x4>;
			device_type = "serial";
			port-number = <0x0>;
		};

		spi0: spi@e0006000 {
			compatible = "xlnx,zynq-spi-r1p6";
			reg = <0xe0006000 0x1000>;
			status = "okay";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x1a 0x4>;
			clocks = <0x1 0x19 0x1 0x22>;
			clock-names = "ref_clk", "pclk";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			is-decoded-cs = <0x1>;
			num-cs = <0x5>;

			spidev@0 {
				compatible = "spidev";
				reg = <0x0>;
				spi-max-frequency = <0xbebc20>;
				spi-cpha;
			};

			spidev@1 {
				compatible = "spidev";
				reg = <0x1>;
				spi-max-frequency = <0xbebc20>;
				spi-cpha;
			};

			spidev@2 {
				compatible = "spidev";
				reg = <0x2>;
				spi-max-frequency = <0xbebc20>;
				spi-cpha;
			};

			spidev@3 {
				compatible = "spidev";
				reg = <0x3>;
				spi-max-frequency = <0xbebc20>;
				spi-cpha;
			};

			spidev@4 {
				compatible = "spidev";
				reg = <0x4>;
				spi-max-frequency = <0xbebc20>;
				spi-cpha;
			};
		};

		spi1: spi@e0007000 {
			compatible = "xlnx,zynq-spi-r1p6";
			reg = <0xe0007000 0x1000>;
			status = "disabled";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x31 0x4>;
			clocks = <0x1 0x1a 0x1 0x23>;
			clock-names = "ref_clk", "pclk";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};

		qspi: spi@e000d000 {
			clock-names = "ref_clk", "pclk";
			clocks = <0x1 0xa 0x1 0x2b>;
			compatible = "xlnx,zynq-qspi-1.0";
			status = "okay";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x13 0x4>;
			reg = <0xe000d000 0x1000>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			is-dual = <0x0>;
			num-cs = <0x1>;
			spi-rx-bus-width = <0x4>;
			spi-tx-bus-width = <0x4>;

			flash@0 {
				compatible = "n25q128a13";
				reg = <0x0>;
				spi-tx-bus-width = <0x1>;
				spi-rx-bus-width = <0x4>;
				spi-max-frequency = <0x2faf080>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;

				partition@qspi-fsbl {
					label = "cx-common";
					reg = <0x0 0x700000>;
				};

				partition@qspi-spare {
					label = "reserved0";
					reg = <0x700000 0x600000>;
				};

				partition@qspi-common {
					label = "reserved1";
					reg = <0xd00000 0x2e0000>;
				};

				partition@qspi-u-boot-env {
					label = "u-boot-env";
					reg = <0xfe0000 0x20000>;
				};
			};
		};

		smcc: memory-controller@e000e000 {
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			status = "disabled";
			clock-names = "memclk", "aclk";
			clocks = <0x1 0xb 0x1 0x2c>;
			compatible = "arm,pl353-smc-r2p1";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x12 0x4>;
			ranges;
			reg = <0xe000e000 0x1000>;

			nand0: flash@e1000000 {
				status = "disabled";
				compatible = "arm,pl353-nand-r2p1";
				reg = <0xe1000000 0x1000000>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
			};

			nor0: flash@e2000000 {
				status = "disabled";
				compatible = "cfi-flash";
				reg = <0xe2000000 0x2000000>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
			};
		};

		gem0: ethernet@e000b000 {
			compatible = "cdns,zynq-gem", "cdns,gem";
			reg = <0xe000b000 0x1000>;
			status = "okay";
			interrupts = <0x0 0x16 0x4>;
			clocks = <0x1 0x1e 0x1 0x1e 0x1 0xd>;
			clock-names = "pclk", "hclk", "tx_clk";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			phy-reset-gpio = <0x5 0xb 0x0>;
			phy-reset-active-low;
			phy-mode = "rgmii-id";
			xlnx,ptp-enet-clock = <0x7735940>;
		};

		gem1: ethernet@e000c000 {
			compatible = "cdns,zynq-gem", "cdns,gem";
			reg = <0xe000c000 0x1000>;
			status = "disabled";
			interrupts = <0x0 0x2d 0x4>;
			clocks = <0x1 0x1f 0x1 0x1f 0x1 0xe>;
			clock-names = "pclk", "hclk", "tx_clk";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};

		sdhci0: sdhci@e0100000 {
			compatible = "arasan,sdhci-8.9a";
			status = "okay";
			clock-names = "clk_xin", "clk_ahb";
			clocks = <0x1 0x15 0x1 0x20>;
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x18 0x4>;
			reg = <0xe0100000 0x1000>;
			xlnx,has-cd = <0x1>;
			xlnx,has-power = <0x0>;
			xlnx,has-wp = <0x0>;
		};

		sdhci1: sdhci@e0101000 {
			compatible = "arasan,sdhci-8.9a";
			status = "disabled";
			clock-names = "clk_xin", "clk_ahb";
			clocks = <0x1 0x16 0x1 0x21>;
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x2f 0x4>;
			reg = <0xe0101000 0x1000>;
		};

		slcr: slcr@f8000000 {
			u-boot,dm-pre-reloc;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
			reg = <0xf8000000 0x1000>;
			ranges;
			linux,phandle = <0x6>;
			phandle = <0x6>;

			clkc: clkc@100 {
				u-boot,dm-pre-reloc;
				#clock-cells = <0x1>;
				compatible = "xlnx,ps7-clkc";
				fclk-enable = <0x1>;
				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
				reg = <0x100 0x100>;
				ps-clk-frequency = <0x1fca055>;
				linux,phandle = <0x1>;
				phandle = <0x1>;
			};

			rstc: rstc@200 {
				compatible = "xlnx,zynq-reset";
				reg = <0x200 0x48>;
				#reset-cells = <0x1>;
				syscon = <0x6>;
			};

			pinctrl0: pinctrl@700 {
				compatible = "xlnx,pinctrl-zynq";
				reg = <0x700 0x200>;
				syscon = <0x6>;
			};
		};

		dmac_s: dmac@f8003000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0xf8003000 0x1000>;
			interrupt-parent = <0x4>;
			interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
			interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
			#dma-cells = <0x1>;
			#dma-channels = <0x8>;
			#dma-requests = <0x4>;
			clocks = <0x1 0x1b>;
			clock-names = "apb_pclk";
		};

		devcfg: devcfg@f8007000 {
			compatible = "xlnx,zynq-devcfg-1.0";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x8 0x4>;
			reg = <0xf8007000 0x100>;
			clocks = <0x1 0xc 0x1 0xf 0x1 0x10 0x1 0x11 0x1 0x12>;
			clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
			syscon = <0x6>;
			linux,phandle = <0x3>;
			phandle = <0x3>;
		};

		efuse: efuse@f800d000 {
			compatible = "xlnx,zynq-efuse";
			reg = <0xf800d000 0x20>;
		};

		global_timer: timer@f8f00200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0xf8f00200 0x20>;
			interrupts = <0x1 0xb 0x301>;
			interrupt-parent = <0x4>;
			clocks = <0x1 0x4>;
		};

		ttc0: timer@f8001000 {
			interrupt-parent = <0x4>;
			interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
			compatible = "cdns,ttc";
			clocks = <0x1 0x6>;
			reg = <0xf8001000 0x1000>;
		};

		ttc1: timer@f8002000 {
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
			compatible = "cdns,ttc";
			clocks = <0x1 0x6>;
			reg = <0xf8002000 0x1000>;
		};

		scutimer: timer@f8f00600 {
			interrupt-parent = <0x4>;
			interrupts = <0x1 0xd 0x301>;
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xf8f00600 0x20>;
			clocks = <0x1 0x4>;
		};

		usb0: usb@e0002000 {
			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
			status = "okay";
			clocks = <0x1 0x1c>;
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x15 0x4>;
			reg = <0xe0002000 0x1000>;
			phy_type = "ulpi";
			usb-reset = <0x5 0xc 0x0>;
		};

		usb1: usb@e0003000 {
			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
			status = "disabled";
			clocks = <0x1 0x1d>;
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x2c 0x4>;
			reg = <0xe0003000 0x1000>;
			phy_type = "ulpi";
		};

		watchdog0: watchdog@f8005000 {
			clocks = <0x1 0x2d>;
			compatible = "cdns,wdt-r1p2";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x9 0x1>;
			reg = <0xf8005000 0x1000>;
			timeout-sec = <0xa>;
		};

		reserved-driver@0 {
			compatible = "xlnx,reserved-memory";
			memory-region = <0x7>;
		};
	};

	amba_pl: amba_pl {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		compatible = "simple-bus";
		ranges;

		axi_gps_uartlite: serial@42c00000 {
			clock-names = "s_axi_aclk";
			clocks = <0x1 0xf>;
			compatible = "xlnx,xps-uartlite-1.00.a";
			current-speed = <0x1c200>;
			device_type = "serial";
			interrupt-names = "interrupt";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x1d 0x1>;
			port-number = <0x2>;
			reg = <0x42c00000 0x10000>;
			xlnx,baudrate = <0x1c200>;
			xlnx,data-bits = <0x8>;
			xlnx,odd-parity = <0x0>;
			xlnx,s-axi-aclk-freq-hz-d = "200.0";
			xlnx,use-parity = <0x0>;
		};

		axi_rif: axi_epc@40600000 {
			compatible = "xlnx,axi-epc-2.0";
			reg = <0x40600000 0x10000>;
			xlnx,num-peripherals = <0x1>;
			xlnx,prh-clk-period-ps = <0x4e20>;
			xlnx,prh-clk-support = <0x0>;
			xlnx,prh-max-adwidth = <0x20>;
			xlnx,prh-max-awidth = <0x3>;
			xlnx,prh-max-dwidth = <0x20>;
			xlnx,prh0-addr-th = <0x0>;
			xlnx,prh0-addr-tsu = <0x0>;
			xlnx,prh0-ads-width = <0x0>;
			xlnx,prh0-awidth = <0x3>;
			xlnx,prh0-bus-multiplex = <0x0>;
			xlnx,prh0-csn-th = <0x0>;
			xlnx,prh0-csn-tsu = <0x0>;
			xlnx,prh0-data-th = <0x0>;
			xlnx,prh0-data-tinv = <0x0>;
			xlnx,prh0-data-tout = <0x0>;
			xlnx,prh0-data-tsu = <0x0>;
			xlnx,prh0-dwidth = <0x20>;
			xlnx,prh0-dwidth-match = <0x0>;
			xlnx,prh0-fifo-access = <0x0>;
			xlnx,prh0-fifo-offset = <0x0>;
			xlnx,prh0-rd-cycle = <0x0>;
			xlnx,prh0-rdn-width = <0x0>;
			xlnx,prh0-rdy-tout = <0x0>;
			xlnx,prh0-rdy-width = <0x0>;
			xlnx,prh0-sync = <0x1>;
			xlnx,prh0-wr-cycle = <0x0>;
			xlnx,prh0-wrn-width = <0x0>;
			xlnx,prh1-addr-th = <0x0>;
			xlnx,prh1-addr-tsu = <0x0>;
			xlnx,prh1-ads-width = <0x0>;
			xlnx,prh1-awidth = <0x20>;
			xlnx,prh1-bus-multiplex = <0x0>;
			xlnx,prh1-csn-th = <0x0>;
			xlnx,prh1-csn-tsu = <0x0>;
			xlnx,prh1-data-th = <0x0>;
			xlnx,prh1-data-tinv = <0x0>;
			xlnx,prh1-data-tout = <0x0>;
			xlnx,prh1-data-tsu = <0x0>;
			xlnx,prh1-dwidth = <0x20>;
			xlnx,prh1-dwidth-match = <0x0>;
			xlnx,prh1-fifo-access = <0x0>;
			xlnx,prh1-fifo-offset = <0x0>;
			xlnx,prh1-rd-cycle = <0x0>;
			xlnx,prh1-rdn-width = <0x0>;
			xlnx,prh1-rdy-tout = <0x0>;
			xlnx,prh1-rdy-width = <0x0>;
			xlnx,prh1-sync = <0x0>;
			xlnx,prh1-wr-cycle = <0x0>;
			xlnx,prh1-wrn-width = <0x0>;
			xlnx,prh2-addr-th = <0x0>;
			xlnx,prh2-addr-tsu = <0x0>;
			xlnx,prh2-ads-width = <0x0>;
			xlnx,prh2-awidth = <0x20>;
			xlnx,prh2-bus-multiplex = <0x0>;
			xlnx,prh2-csn-th = <0x0>;
			xlnx,prh2-csn-tsu = <0x0>;
			xlnx,prh2-data-th = <0x0>;
			xlnx,prh2-data-tinv = <0x0>;
			xlnx,prh2-data-tout = <0x0>;
			xlnx,prh2-data-tsu = <0x0>;
			xlnx,prh2-dwidth = <0x20>;
			xlnx,prh2-dwidth-match = <0x0>;
			xlnx,prh2-fifo-access = <0x0>;
			xlnx,prh2-fifo-offset = <0x0>;
			xlnx,prh2-rd-cycle = <0x0>;
			xlnx,prh2-rdn-width = <0x0>;
			xlnx,prh2-rdy-tout = <0x0>;
			xlnx,prh2-rdy-width = <0x0>;
			xlnx,prh2-sync = <0x0>;
			xlnx,prh2-wr-cycle = <0x0>;
			xlnx,prh2-wrn-width = <0x0>;
			xlnx,prh3-addr-th = <0x0>;
			xlnx,prh3-addr-tsu = <0x0>;
			xlnx,prh3-ads-width = <0x0>;
			xlnx,prh3-awidth = <0x20>;
			xlnx,prh3-bus-multiplex = <0x0>;
			xlnx,prh3-csn-th = <0x0>;
			xlnx,prh3-csn-tsu = <0x0>;
			xlnx,prh3-data-th = <0x0>;
			xlnx,prh3-data-tinv = <0x0>;
			xlnx,prh3-data-tout = <0x0>;
			xlnx,prh3-data-tsu = <0x0>;
			xlnx,prh3-dwidth = <0x20>;
			xlnx,prh3-dwidth-match = <0x0>;
			xlnx,prh3-fifo-access = <0x0>;
			xlnx,prh3-fifo-offset = <0x0>;
			xlnx,prh3-rd-cycle = <0x0>;
			xlnx,prh3-rdn-width = <0x0>;
			xlnx,prh3-rdy-tout = <0x0>;
			xlnx,prh3-rdy-width = <0x0>;
			xlnx,prh3-sync = <0x0>;
			xlnx,prh3-wr-cycle = <0x0>;
			xlnx,prh3-wrn-width = <0x0>;
			xlnx,s-axi-clk-period-ps = <0x1388>;
		};
	};

	leds {
		compatible = "gpio-leds";

		service {
			label = "service";
			gpios = <0x5 0xa 0x1>;
		};

		alarm {
			label = "alarm";
			gpios = <0x5 0x9 0x1>;
		};

		system_wdt {
			label = "system_wdt";
			gpios = <0x5 0x7 0x0>;
			linux,default-trigger = "heartbeat";
		};
	};

	reserved-memory {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges;

		reserved: buffer@0 {
			reg = <0x38000000 0x8000000>;
			linux,phandle = <0x7>;
			phandle = <0x7>;
		};
	};

	chosen {
		bootargs = "earlycon earlyprintk root=/dev/ram rw ramdisk_size=0x4000000";
		stdout-path = "serial0:115200n8";
	};

	aliases {
		ethernet0 = "/amba/ethernet@e000b000";
		serial0 = "/amba/serial@e0001000";
		serial1 = "/amba/serial@e0000000";
		serial2 = "/amba_pl/serial@42c00000";
		spi0 = "/amba/spi@e000d000";
		spi1 = "/amba/spi@e0006000";
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x40000000>;
	};
};

and the console output on an attempted boot

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 4.14.0-cellXica-sc6-xilinx (paul@npm-vaio2) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11-rc1)) #1 SMP PREEMPT Thu Aug 9 11:12:26 BST 2018
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: cellXica SC6 Platform
earlycon: cdns0 at MMIO 0xe0001000 (options '115200n8')
bootconsole [cdns0] enabled
Memory policy: Data cache writealloc
cma: Reserved 16 MiB at 0x37000000
percpu: Embedded 16 pages/cpu @ef7cd000 s34764 r8192 d22580 u65536
Built 1 zonelists, mobility grouping on.  Total pages: 260608
Kernel command line: earlycon earlyprintk root=/dev/ram rw ramdisk_size=0x4000000
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 876464K/1048576K available (7168K kernel code, 247K rwdata, 1708K rodata, 1024K init, 171K bss, 155728K reserved, 16384K cma-reserved, 114688K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
    lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc0800000   (8160 kB)
      .init : 0xc0a00000 - 0xc0b00000   (1024 kB)
      .data : 0xc0b00000 - 0xc0b3df00   ( 248 kB)
       .bss : 0xc0b3df00 - 0xc0b68b9c   ( 172 kB)
Preemptible hierarchical RCU implementation.
        Tasks RCU enabled.
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to f0800000
slcr mapped to f0802000
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
zynq_clock_init: clkc starts at f0802100
Zynq clock init
sched_clock: 64 bits at 374MHz, resolution 2ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x567c8a6b62, max_idle_ns: 440795216687 ns
Switching to timer-based delay loop, resolution 2ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 477809044 ns
timer #0 at f080a000, irq=17
Console: colour dummy device 80x30
console [tty0] enabled
bootconsole [cdns0] disabled
Booting Linux on physical CPU 0x0
Linux version 4.14.0-cellXica-sc6-xilinx (paul@npm-vaio2) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11-rc1)) #1 SMP PREEMPT Thu Aug 9 11:12:26 BST 2018
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: cellXica SC6 Platform
earlycon: cdns0 at MMIO 0xe0001000 (options '115200n8')
bootconsole [cdns0] enabled
Memory policy: Data cache writealloc
cma: Reserved 16 MiB at 0x37000000
percpu: Embedded 16 pages/cpu @ef7cd000 s34764 r8192 d22580 u65536
Built 1 zonelists, mobility grouping on.  Total pages: 260608
Kernel command line: earlycon earlyprintk root=/dev/ram rw ramdisk_size=0x4000000
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 876464K/1048576K available (7168K kernel code, 247K rwdata, 1708K rodata, 1024K init, 171K bss, 155728K reserved, 16384K cma-reserved, 114688K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
    lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc0800000   (8160 kB)
      .init : 0xc0a00000 - 0xc0b00000   (1024 kB)
      .data : 0xc0b00000 - 0xc0b3df00   ( 248 kB)
       .bss : 0xc0b3df00 - 0xc0b68b9c   ( 172 kB)
Preemptible hierarchical RCU implementation.
        Tasks RCU enabled.
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to f0800000
slcr mapped to f0802000
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
zynq_clock_init: clkc starts at f0802100
Zynq clock init
sched_clock: 64 bits at 374MHz, resolution 2ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x567c8a6b62, max_idle_ns: 440795216687 ns
Switching to timer-based delay loop, resolution 2ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 477809044 ns
timer #0 at f080a000, irq=17
Console: colour dummy device 80x30
console [tty0] enabled
bootconsole [cdns0] disabled
Calibrating delay loop (skipped), value calculated using timer frequency.. 749.99 BogoMIPS (lpj=3749999)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100060
Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs ...
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
smp: Brought up 1 node, 2 CPUs
SMP: Total of 2 processors activated (1499.99 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
random: get_random_u32 called from bucket_table_alloc+0x114/0x23c with crng_init=0
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes)
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
random: fast init done
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor menu
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0xf0880000
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
e0000000.serial: ttyPS1 at MMIO 0xe0000000 (irq = 25, base_baud = 6249999) is a xuartps
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 26, base_baud = 6249999) is a xuartps
console [ttyPS0] enabled
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
media: Linux media interface: v0.10
Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
FPGA manager framework
fpga-region fpga-full: FPGA Region probed
Advanced Linux Sound Architecture Driver Initialized.
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Trying to unpack rootfs image as initramfs...
rootfs image is not initramfs (no cpio magic); looks like an initrd
Freeing initrd memory: 4292K
hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
workingset: timestamp_bits=30 max_order=18 bucket_order=0
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
jffs2: version 2.2. (NAND) (SUMMARY)  �© 2001-2006 Red Hat, Inc.
JFS: nTxBlock = 7008, nTxLock = 56071
bounce: pool size: 64 pages
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
io scheduler mq-deadline registered
io scheduler kyber registered
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16

### at this point the kernel hangs and becomes unresponsive requiring a reboot ###

 

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Visitor
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Registered: ‎08-09-2018

Re: ZYNQ 7000 hangs on boot after adding uartlite

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So it appears that we found the problem. We had set up the FPGA to be flashed after the call to initialize the driver which meant that the driver was trying to communicate with an as of yet non-existent device. After loading the FPGA through u-boot the device appears in the dev folder as expected.

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Explorer
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Registered: ‎12-02-2014

Re: ZYNQ 7000 hangs on boot after adding uartlite

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Can you figure out the minimum amount of that code that you have to remove?  (comment out each line one at a time).

 

This debug approach might not work super well though, because you're basically forcing that assign function to fail.

 

My guess would be that you have an interrupt or memory conflict.

 

 

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Registered: ‎08-09-2018

Re: ZYNQ 7000 hangs on boot after adding uartlite

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Yes, I've tried reducing the code to the minimum that needs to be commented out but there seem to be various combinations that enable a boot or cause a hang (some combinations cause a kernel panic). However, I don't think this is the correct way to debug as commenting the code is only essentially disabling the correct initialization procedure. This was only to highlight that it is an issue with the uartlite and not some other problem in the kernel.

 

I have attempted to debug the kernel by adding 'printk' statements to find the spot where it hangs. The hang seems to be caused by some form of interrupt because at the point of hanging I had several concurrent printk statements and only the first would be executed. This interrupt however is not caused by the uartlite itself as I have tried changing the design in vivado to disconnect the irq_f2p from the uart and tie it to 0 and the same problem occurs.

 

I've read some comments on other posts which suggest the hang may be caused by the driver attempting to access the axi bus which doesn't have a timeout. Is there any way of verifying that the port or axi bus has been correctly configured?

 

Has anyone been able to get the uartlite working with linux 4.14 and vivado 2018.1 at all?

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Registered: ‎12-02-2014

Re: ZYNQ 7000 hangs on boot after adding uartlite

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In your device tree, you had the interrupt set to 0x1d.  Can you make sure that is correct?

 

EDIT:

 

Just looking at how the ISR is setup:

do {
spin_lock_irqsave(&port->lock, flags);
stat = uart_in32(ULITE_STATUS, port);
busy = ulite_receive(port, stat);
busy |= ulite_transmit(port, stat);
spin_unlock_irqrestore(&port->lock, flags);
n++;
} while (busy);

 

if ulite_receive and ulite_transmit constantly return busy as non-zero, you will hang here indefinitely.  You could print the value of n here after the n++ to see if this is what's happening. (you may want to put some kind of udelay after the printk to ensure that it gets the opportunity to print.

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Re: ZYNQ 7000 hangs on boot after adding uartlite

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It doesn't appear to be an issue with the ISR as it is never even called. I have a printk at the start of the ISR and in the loop (both with delay) and neither show up.

 

Interrupt 0x1d (or 29) is correct.

The three numbers in the interrupts field

1. whether the device is SPI (0) or PPI (1); in this case it is SPI

2. the interrupt number for the device. To this is added 32 (SPI) or 16 (PPI);  29 + 32 = 61

3. the interrupt type; 1 for rising edge

 

The first number on the range of the IRQ_F2P pin on the processor is 61 and the uartlite is setup to up to use this as shown in the following line from the xparams.h file.

#define XPAR_FABRIC_AXI_GPS_UARTLITE_INTERRUPT_INTR 61U

Replacing 0x1d with a smaller number let's the device boot but the uartlite is not properly registered as it fails to assign an irq number to it.

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Re: ZYNQ 7000 hangs on boot after adding uartlite

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So it appears that we found the problem. We had set up the FPGA to be flashed after the call to initialize the driver which meant that the driver was trying to communicate with an as of yet non-existent device. After loading the FPGA through u-boot the device appears in the dev folder as expected.

View solution in original post

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Registered: ‎12-02-2014

Re: ZYNQ 7000 hangs on boot after adding uartlite

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Glad you solved it!

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