07-24-2018 02:02 AM
In my custmer Zynq 7020 board, The KSZ9031 can not work in 1000Mbps mode.But in 1000Mbps mode, the link up status can be detected, the data switching is not work. Fristly,the cable with 100Mpbs switch is used to connect the board, the 100Mbps is link up,and PING also can be executed correctlly. Secondly ,the cable with 1000Mpbs switch is used to connect the board, the link up status is coming out, and the 125Mbps clock can also be detected，but PING can not be executed, and data switching break;
The result is confusing me. I can't tell where the problem is. MAC<->PHY or PHY<->Rj45 ? Please help .
My enviroment is as follows.
The kernel verison is 2017.1.
Etherent phy is KSZ9031 RNX rgmii mode.
The Rj45 is made as 1000Mbps mode.
07-24-2018 02:16 AM
Monitor the Registers of the PHY to see if the link goes down. I don't think this is very likely if the pcb and cable are in proper condition.
Have you set up the RGMII correctly? How do you add the delay between clock and data?
The delay can usually be added through either the I/ODELAYs (your Zynq only has IDELAY), through a PLL, through a long PCB-Trace for the clock, or through a delay-setting in the PHY. The last one is usually the easiest one to get right.
How is the Phy attached - MIO or EMIO-Pins.
07-24-2018 02:56 AM
I don not think the KS9031 registers is wrong. Please help check it. I have up it.The KSZ9031 can link up in 1000Mbps , but the data excharge failed. The ksz9031 is connected to MIO-pins. I think the rgmii mode is set up RGMII correctly, because the in 100mbps mode the net is work very well.I do not add any IDELAYs , may be I check it fristly.
07-24-2018 03:34 AM
Did you add the Delay of 2ns on the clock-lines on the pcb? If not, then the only option left is to enable the delays in the PHY (if supported).
On 100Mbps, that bus is only running at 25MHz and the setup/hold-time is a lot more loose.
07-25-2018 11:58 PM
07-26-2018 12:05 AM
07-26-2018 12:43 AM
Did you measure the RXD-Bits relative to the RXC and the TXD-Bits relative to the TXC? You should have a delay of 2ns between both rising and filling edge of the clock and any transition of the data.
If there is no delay, you need to use the internal delay in the PHY. If the Phy cannot do that, you have a problem and might need a new revision of your pcb that adds these delays on the traces.