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doonny
Explorer
Explorer
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Registered: ‎07-28-2013

Zynq-7000 boot hangs on xintc_write (IRQ)

I am trying to manually build the linux image for a reference zc706 xsa design, which is provided as the reference vitis platform design from github: https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/master/Xilinx_Official_Platforms/xilinx_zc706_base

The axi_int configuration is as follow:

vivado.PNG

DeviceTree is set as follow:

---------------------------------------------------

/include/ "system-conf.dtsi"
/ {
};

&amba_pl {
/delete-node/ interrupt-controller@70000000;
/delete-node/ misc_clk_0;
};

&amba {
axi_intc_0: interrupt-controller@70000000 {
#interrupt-cells = <2>;
clock-names = "s_axi_aclk";
clocks = <&misc_clk_0>;
compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a";
interrupt-controller ;
interrupt-names = "irq";
interrupt-parent = <&intc>;
interrupts = <0 29 1>;
reg = <0x70000000 0x10000>;
xlnx,kind-of-intr = <0x1>;
xlnx,num-intr-inputs = <0x20>;
};

misc_clk_0: misc_clk_0 {
#clock-cells = <0>;
clock-frequency = <165972222>;
compatible = "fixed-clock";
};

zyxclmm_drm {
compatible = "xlnx,zocl";
status = "okay";
interrupt-parent = <&axi_intc_0>;
interrupts = <0 4>, <1 4>, <2 4>, 4>,
<4 4>, <5 4>, <6 4>, <7 4>,
<8 4>, <9 4>, <10 4>, <11 4>,
<12 4>, <13 4>, <14 4>, <15 4>,
<16 4>, <17 4>, <18 4>, <19 4>,
<20 4>, <21 4>, <22 4>, <23 4>,
<24 4>, <25 4>, <26 4>, <27 4>,
<28 4>, <29 4>, <30 4>, <31 4>;
};
};

---------------------------------------------------

Bootup hangs as follow:

Booting Linux on physical CPU 0x0
Linux version 5.4.0-xilinx-v2020.1 (oe-user@oe-host) (gcc version 9.2.0 (GCC)) #1 SMP PREEMPT Tue Jan 12 03:40:32 UTC 2021
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: Zynq ZC706 Development Board
earlycon: cdns0 at MMIO 0xe0001000 (options '115200n8')
printk: bootconsole [cdns0] enabled
Memory policy: Data cache writealloc
cma: Reserved 256 MiB at 0x30000000
percpu: Embedded 15 pages/cpu s30860 r8192 d22388 u61440
Built 1 zonelists, mobility grouping on. Total pages: 260416
Kernel command line: earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait cma=256M
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes, linear)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
mem auto-init: stack:off, heap alloc:off, heap free:off
Memory: 766144K/1048576K available (6144K kernel code, 214K rwdata, 1828K rodata, 1024K init, 131K bss, 20288K reserved, 262144K cma-reserved, 0K highmem)
rcu: Preemptible hierarchical RCU implementation.
rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to (ptrval)
slcr mapped to (ptrval)
irq-xilinx: /amba/interrupt-controller@70000000: num_irq=32, sw_irq=0, edge=0x1
8<--- cut here ---
Unhandled fault: imprecise external abort (0xc06) at 0x00000000
pgd = (ptrval)
[00000000] *pgd=00000000
Internal error: Oops - BUG: c06 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.4.0-xilinx-v2020.1 #1
Hardware name: Xilinx Zynq Platform
PC is at xintc_write+0x6c/0x80
LR is at xil_intc_initial_setup+0x24/0xbc
pc : [<c033f57c>] lr : [<c033f7a4>] psr: 600000d3
sp : c0a01f20 ip : 00000000 fp : c0866af4
r10: 00000122 r9 : 00000100 r8 : c0a01f74
r7 : ef6ee47c r6 : f081000c r5 : ffffffff r4 : ef004380
r3 : 00000000 r2 : ffffffff r1 : f0810000 r0 : ef004380
Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment none
Control: 18c5387d Table: 0000404a DAC: 00000051
Process swapper/0 (pid: 0, stack limit = 0x(ptrval))
Stack: (0xc0a01f20 to 0xc0a02000)
1f20: ef004380 00000000 ef6f66d0 c033f7a4 ef004380 00000000 ef6f66d0 ef6ee47c
1f40: c0a01f74 c09160e0 c0724a48 ef004380 00000000 c0a03c48 00000122 ef0043c0
1f60: ef6ee47c c0a01f74 c0a01f7c c0921398 00000000 c0a01f74 c0a01f74 c0a01f7c
1f80: c0a01f7c c0a03c48 00000000 c092da30 c0a03c40 c0a35800 00000000 c0a35800
1fa0: 00000001 c092da40 00000000 c0903558 c0a45388 c0900b3c ffffffff ffffffff
1fc0: 00000000 c0900578 00000000 c092da40 00000000 c0a03c48 c0900330 00000051
1fe0: 10c0387d 00000000 1fff6000 413fc090 18c5387d 00000000 00000000 00000000
[<c033f57c>] (xintc_write) from [<c033f7a4>] (xil_intc_initial_setup+0x24/0xbc)
[<c033f7a4>] (xil_intc_initial_setup) from [<c09160e0>] (xilinx_intc_of_init+0x160/0x2f8)
[<c09160e0>] (xilinx_intc_of_init) from [<c0921398>] (of_irq_init+0x1e4/0x288)
[<c0921398>] (of_irq_init) from [<c0903558>] (init_IRQ+0x68/0x78)
[<c0903558>] (init_IRQ) from [<c0900b3c>] (start_kernel+0x224/0x440)
[<c0900b3c>] (start_kernel) from [<00000000>] (0x0)
Code: e8bd8070 e5941000 e0816006 f57ff04e (ebf74f8e)
random: get_random_bytes called from init_oops_id+0x20/0x3c with crng_init=0
---[ end trace 0000000000000000 ]---
Kernel panic - not syncing: Attempted to kill the idle task!
---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]---

------------------------------------------------------------------

It seems to related to the axi_intc, but not sure how to fix it.

 

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3 Replies
gunner1886
Visitor
Visitor
389 Views
Registered: ‎02-04-2021

Hi @doonny  ,
Have you ever found a way to fix it. I've got the same issue for PicoZed 7z020.

I managed to build an image using reference bsp from Avnet. And that boots fine.

Then I imported my own hardware configuration (.xsa) (previously exported from Vivado). I call:
$ petalinux-config --get-hw-description=<path-to-directory-containing-hardware description-file> and I do some basic configuration here.

Then I call: 
petalinux-build,
which builds successfully.

At the end I generate boot image:
$ petalinux-package --boot --fsbl <FSBL image> --fpga <FPGA bitstream> --u-boot

I get the same errors as in the post above. 
I something is definitely wrong with my hardware since replacing my bitstream with the one from reference design build makes my system booting.
This is my Vivado 2020.1 block design:

gunner1886_0-1612515900917.png

 

Does anyone know if I missed some interrupt configuration?

 

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doonny
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Explorer
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Registered: ‎07-28-2013

HI @gunner1886 ,please make sure that the output level of the axi_intc is set to "Active High"

gunner1886
Visitor
Visitor
354 Views
Registered: ‎02-04-2021

Thank you @doonny .
However, the thing was I did not know AXI Interrupt Controller was required (at all)
I added it to my Vivado project design and did the rest with petalinux and it worked

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