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Anonymous
Not applicable
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Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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Hi everyone, I already contacted support about this but thought it could be interesting to see if the "Linux on Zynq" community has any input.

 

I'm trying to reload a FPGA bitfile using the Xilinx Linux xdevcfg driver, essentially by just cat:ing the ("bit reversed") bitfile into the /dev/xdevcfg device file. Commit messages for the xdevcfg driver in the Xilinx git repo seems to indicate that this should work. (link)

 

However, after doing this the prog_done signal is never asserted again, so it's not working for me. The same bitfile (without bit reversing) works fine if loaded by the first stage bootloader or via JTAG.

 

Has anyone got this working?

 

Best regards

Johan

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Xilinx Employee
Xilinx Employee
44,241 Views
Registered: ‎02-01-2008

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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As I previously mentioned, use -split option of bootgen. So something like the following:

 

bootgen –image bootimage.bif –split bin –o I boot.bin

 

This will create a top.bit.bin (or whatever the bitfile is). You mention FSBL so I presume you already have a .bif file and have created BOOT.BIN

 

View solution in original post

35 Replies
Xilinx Employee
Xilinx Employee
32,918 Views
Registered: ‎02-01-2008

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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mknod /dev/xdevcfg c 259 0

cat /sys/devices/amba.0/f8007000.devcfg/prog_done       (if returns 1 then PL is programmed)

cat top.bit.bin > /dev/xdevcfg

 

 

The reason the file is top.bit.bin is because I use bootgen with the -split option to do the bit reversing.

 

Anonymous
Not applicable
32,916 Views

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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Thank you for you very speedy ansver :)

 

This is exactly how I did my attempt, except that I used another bit file. Hence, there must be something wrong with my bit file.

 

Do you have any pointers on on how to convert a "normal" bit file (that works with fsbl and JTAG loading) to the proper xdevcfg format, using the Xilinx Design Tools for Windows (or other tools?). I'm pretty sure I missed something here.

 

Thanks in advance,

Johan

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Xilinx Employee
Xilinx Employee
44,242 Views
Registered: ‎02-01-2008

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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As I previously mentioned, use -split option of bootgen. So something like the following:

 

bootgen –image bootimage.bif –split bin –o I boot.bin

 

This will create a top.bit.bin (or whatever the bitfile is). You mention FSBL so I presume you already have a .bif file and have created BOOT.BIN

 

View solution in original post

Anonymous
Not applicable
32,885 Views

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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Success! With a proper bit file it works perfectly on the ZC702 eval board. Thanks for your help.

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Adventurer
Adventurer
32,868 Views
Registered: ‎05-07-2012

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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Will this driver be submitted to the upstream kernel?

 

Also, could we extend it to bit bang load (or use a spi controller to move data) fpga's attached to external processors? I can point you at another driver that uses that to load external fpga's.

 

Philip

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Visitor jonkar
Visitor
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Registered: ‎03-30-2012

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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Hi,

 

I'm a collegue of Johan and as he said we succeeded loading the FPGA using /dev/xdevcfg in linux on the evaluation board zc702 Rev C.

 

The problem is that we have not succeded on our custom boards yet. We have not been able to load the FPGA from neither the FSBL or /dev/xdevcfg. We have only succeded using iMPACT + JTAG. Since we can load the FPGA via JTAG the bit file must be ok.

 

The error message from FSBL indicates that there is an FPGA config time out.

 

Do you have any good ideas on what can cause these problems? Can it be a board design issue?

 

Please give us some advise on how to solve this issue.

 

 

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Xilinx Employee
Xilinx Employee
32,835 Views
Registered: ‎09-10-2008

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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Sounds like you should open a web case for this problem.  I doubt it's a board issue but could be something is configured wrong due to different clock frequencies, etc...

 

Thanks.

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Xilinx Employee
Xilinx Employee
32,832 Views
Registered: ‎09-10-2008

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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Hi Philip,

At some point yes we hope to get to pushing upstream again. I think the driver would be completely different for an external FPGA as this uses a Zynq specific engine to load the data.

Thanks.
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Visitor jonkar
Visitor
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Registered: ‎03-30-2012

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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We might have found the root cause on our custom boards. When we designed our boards we used the february version of the UG865 document which says that pin R6 on our XC7Z020-1CLG-400CES is RSVDGND. In the new version of UG865 pin R6 is RSVDVCC.

 

We have connected R6 to ground.

 

Johnmcd and linnj: What do you think, is it likely that this is the root cause?

 

We will try to patch our custom boards, but since we have to lift the BGA it is a high risc operation and it might take some time.

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Xilinx Employee
Xilinx Employee
18,750 Views
Registered: ‎02-01-2008

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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Those pins are mode pins for the PL and very related to configuration. The change between versions of the user guide was due to problems such as what you are seeing.

 

Emails where sent to the field regarding this change and updates were posted on the lounge. So somehow we missed you.

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Adventurer
Adventurer
18,725 Views
Registered: ‎05-07-2012

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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I disagree the driver would be completly differenet for an external fgpa.

 

Consider that all user space cares about is writing a bin file to a device node that corresponds to the target fpga.

 

The driver will need to be aware of the type of fpga connected and chose (via compile option or runtime slection) the specific protocol to load the fpga. I'm sure you would get push back from reviewers if you submit a driver for every possible way to connect an fpga to a processor :)

 

See:

 

http://ncrmnt.org/wp/2011/11/18/configuring-a-xilinx-fpga-from-arm/#more-701

 

for a driver that bit bangs the image. I'd revise that driver to use the gpio spi code to move the data to the fpga, so people that attached the fpga to a hard controller could change the spi resource.

 

Philip

 

Philip

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Adventurer
Adventurer
18,614 Views
Registered: ‎05-07-2012

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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I made a bif file with this in it:

 

fpga_image:
{
   system_stub.bit
} 

and run

$ bootgen -image fpga.bif -split bin -o I fpga.bin
Segmentation fault (core dumped)

Any hints on getting abin file I can load into the zc702 from Linux?

 

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Xilinx Employee
Xilinx Employee
18,593 Views
Registered: ‎09-10-2008

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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You may want to file a webcase on that one. I'm not sure what version of tools you are using.

 

Sorry.

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Adventurer
Adventurer
18,591 Views
Registered: ‎05-07-2012

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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14.1. Is there a better way to convert the bitfile into a bin file that will load into zynq?
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Xilinx Employee
Xilinx Employee
18,588 Views
Registered: ‎11-28-2007

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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I once used:

promgen -b -w -p bin -data_width 32 -u 0 system_stub.bit -o system_stub.bit.bin

 

Not tested with Linux, but bare-metal with the devcfg driver was successful.

The advantage is, promgen reports the length which can be set for the dma.

Peter

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Adventurer
Adventurer
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Registered: ‎05-07-2012

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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The promgen command worked on Linux also. Thanks. Now I need to start doing hard stuff :)
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Scholar milosoftware
Scholar
18,106 Views
Registered: ‎10-26-2012

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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bootgen crashes on my system when I try to use it to generate a bin file:

$ cat bootimage.bif 
the_ROM_image: {
  /home/mike/zynq/xilinx-image/cf_adv7511_zc702.bit
}
$ bootgen -image bootimage.bif -split bin -o I fpga.bin
Segmentation fault
$ 

I have also tried using a tool that I wrote for another FPGA, which extracts a bin file that looks just fine, but then the bin file fails to load.

The .bit file given works okay when passed to bootgen for the bootloader.

Help?
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Xilinx Employee
Xilinx Employee
18,093 Views
Registered: ‎12-08-2011

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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have you tried using promgen?

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Xilinx Employee
Xilinx Employee
18,086 Views
Registered: ‎02-01-2008

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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Bootgen is picky. It expects to see an elf first since FSBL is expected to run. So either you can create a fsbl or hello world elf as a dummy file and add that to your bootgen config file and then just throw away the bootimage.bin file created after the split

 

Or

 

as Chris mentions, you can use promgen.

 

Since the Zynq interface is 32bits, you need the bytes swapped. So the promgen command is:

 

promgen -w -b -p bin -o top.promgen.bin -u 0 top.bit -data_width 32

 

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Scholar milosoftware
Scholar
16,162 Views
Registered: ‎10-26-2012

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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I looked at the files with a HEX editor, and noticed that bootgen reversed the bytes in each 4-byte word in the file. So if I do the same in my tool, it should work alright and I don't need any extra unknown binaries in the build.

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Visitor yimcli
Visitor
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Registered: ‎06-21-2013

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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Hi,

 

I am using XC706 board. I have a bit file that behave as expected when downloading via the JTAG. Next I use the "promgen -w -b -p bin -o top.promgen.bin -u 0 top.bit -data_width 32" command to generate a bin file. After using the "cat <filename>.bin > /dev/xdevcfg" command to load the FPGA image, the FPGA done pin is not set.

 

I tried a bin file downloaded from Xilinx web site and the same "cat" command can load the FPGA. Any clue about what I may have done wrong?

 

Thanks,

Louis.

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Scholar milosoftware
Scholar
15,257 Views
Registered: ‎10-26-2012

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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Could be a bug in the tool or so. I hit my head on that too many times, so I cooked my own bit-to-bin conversion program in a few lines of Python.

 

https://github.com/milosoftware/meta-zynq/raw/master/recipes-bsp/fpga/fpga-image/fpga-bit-to-bin.py

 

Just run

 

fpga-bit-to-bin.py --flip input.bit output.bin

 

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Visitor yimcli
Visitor
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Registered: ‎06-21-2013

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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Hi 


kel-lx37:10:28am:~/Vivado/Temp:<113> /usr/local/bin/python2.7.1 fpga-bit-to-bin.py --flip top_level.bit top_level_python.bin
Design name: top_level;UserID=0XFFFFFFFF
Partname 7z045ffg900
Date 2013/08/30
Time 18:37:05
found binary data&colon; 13321404
kel-lx37:10:30am:~/Vivado/Temp:<114>

 

However, when using the "cat" command to load the FPGA, the DONE LED still doesn't turn on.

 

Any suggestion? Thanks,

Louis.

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Scholar milosoftware
Scholar
15,220 Views
Registered: ‎10-26-2012

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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I'd say, try it with a "known good" bitstream. If that works, the conversion tool appears to work fine. We've been using it for months now, for various versions of ISE and Vivado projects (and even competing products), both partial and full bitstreams.

 

Bugs in the Xilinx tools may lead to invalid bitstreams, so if you have a project which triggers that, I think Xilinx will be more than prepared to help you with that.

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Scholar rfs613
Scholar
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Registered: ‎05-28-2013

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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FYI... the 3.10 kernel (Xilinx 14.7 release) now handles "raw" bit files. You don't need to use bootgen -split anymore, the driver will do the necessary conversion automatically.
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Participant sschekall
Participant
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Registered: ‎10-27-2013

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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I am having similar problems on a MicroZed board.

 

zynq> cat system.bin > /dev/xdevcfg

cat: write error: Connection timed out

 

What does this mean? How do I fix it?

 

 

I have included a the /sys

 

zynq> ls -l /sys/bus/platform/drivers/xdevcfg/f8007000.ps7-dev-cfg
total 0
-rw-r--r--    1 root     root          4096 Jan  1 05:49 aes_en_lock
-rw-r--r--    1 root     root          4096 Jan  1 05:49 dbg_lock
lrwxrwxrwx    1 root     root             0 Jan  1 05:49 driver -> ../../../bus/platform/drivers/xdevcfg
-rw-r--r--    1 root     root          4096 Jan  1 05:49 enable_aes
-rw-r--r--    1 root     root          4096 Jan  1 05:49 enable_dap
-rw-r--r--    1 root     root          4096 Jan  1 05:49 enable_dbg_in
-rw-r--r--    1 root     root          4096 Jan  1 05:49 enable_dbg_nonin
-rw-r--r--    1 root     root          4096 Jan  1 05:49 enable_sec_dbg_in
-rw-r--r--    1 root     root          4096 Jan  1 05:49 enable_sec_dbg_nonin
-rw-r--r--    1 root     root          4096 Jan  1 05:49 enable_seu
-rw-r--r--    1 root     root          4096 Jan  1 05:49 is_partial_bitstream
-r--r--r--    1 root     root          4096 Jan  1 05:49 modalias
drwxr-xr-x    2 root     root             0 Jan  1 05:49 power
-rw-r--r--    1 root     root          4096 Jan  1 05:49 prog_done
-rw-r--r--    1 root     root          4096 Jan  1 05:49 seu_lock
lrwxrwxrwx    1 root     root             0 Jan  1 05:49 subsystem -> ../../../bus/platform
-rw-r--r--    1 root     root          4096 Jan  1 05:49 uevent

 

 

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Scholar rfs613
Scholar
14,907 Views
Registered: ‎05-28-2013

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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This means the DMA transfer did not complete within the timeout (1000 ms by default). Normally there is an interrupt when the DMA transfer completes. So either the DMA isn't working, or the interrupt isn't working.

Check /proc/interrupts for IRQ 40, does it show a non-zero count in the 2nd (or 3rd) column? It should increase with each write to /dev/xdevcfg.
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Participant sschekall
Participant
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Registered: ‎10-27-2013

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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OK. So the DMA may not not working?  Or the interrupt isn't working?

 

How is this possible? and ...

How Do I fix it?

 

I'm using the linux kernal from xilinx.

 

cat /proc/versions

Linux version 3.8.0-xilinx (training@localhost.localdomain) (gcc version 4.7.2 (Sourcery CodeBench Lite 2012.09-104) ) #2 SMP PREEMPT Thu Jun 13 10:25:52 PDT 2013

 

 

zynq> cat cpuinfo

processor       : 0 model name      : ARMv7 Processor rev 0 (v7l) BogoMIPS        : 1332.01 Features        : swp half thumb fastmult vfp edsp neon vfpv3 tls CPU implementer : 0x41 CPU architecture: 7 CPU variant     : 0x3 CPU part        : 0xc09 CPU revision    : 0

processor       : 1 model name      : ARMv7 Processor rev 0 (v7l) BogoMIPS        : 1332.01 Features        : swp half thumb fastmult vfp edsp neon vfpv3 tls CPU implementer : 0x41 CPU architecture: 7 CPU variant     : 0x3 CPU part        : 0xc09 CPU revision    : 0

Hardware        : Xilinx Zynq Platform Revision        : 0000 Serial          : 0000000000000000

 

 

zynq> cat interrupts
           CPU0       CPU1
 29:     130569     112477       GIC  twd
 40:          0          0       GIC  xdevcfg
 43:          6          0       GIC  xttcps_clockevent
 46:     220453          0       GIC  f8003000.ps7-dma
 47:     218292          0       GIC  f8003000.ps7-dma
 48:     217708          0       GIC  f8003000.ps7-dma
 49:     217434          0       GIC  f8003000.ps7-dma
 51:          2          0       GIC  e000d000.ps7-qspi
 53:          0          0       GIC  ehci_hcd:usb1
 54:          0          0       GIC  eth0
 56:         57          0       GIC  mmc0
 72:     218466          0       GIC  f8003000.ps7-dma
 73:     216151          0       GIC  f8003000.ps7-dma
 74:     216322          0       GIC  f8003000.ps7-dma
 75:     216581          0       GIC  f8003000.ps7-dma
 82:        611          0       GIC  xuartps
IPI1:          0          0  Timer broadcast interrupts
IPI2:       1359     212055  Rescheduling interrupts
IPI3:          0          0  Function call interrupts
IPI4:         58         48  Single function call interrupts
IPI5:          0          0  CPU stop interrupts
Err:          0

 

 

 

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Scholar rfs613
Scholar
14,874 Views
Registered: ‎05-28-2013

Re: Zynq: Loading bitfile into FPGA from Linux (xdevcfg)

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It's hard to be certain... your /proc/interrupts shows zero interrupts for xdevcfg. So that could indicate that the interrupt is masked/disabled, or it could mean that the DMA is not completing (and therefore not ever generating the interrupt).

Section 6.4.5 of the Zynq Tech Ref Manual describes the bit-stream programming steps. I would suggest checking that the PL has power. Also check your system clock settings.
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