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Visitor kraiskil
Visitor
10,875 Views
Registered: ‎02-05-2016

Zynq USB phy communication issues

Hello,

 

I have a problem using my Zynq (on a Zybo board) as an USB peripheral with the Zynq running Linux.

The problem is that the USB phy chip is detected 'randomly'. On some boots it is detected, on others it is not.

Sometimes a soft reboot helps to have the chip detected on the next boot, sometimes a power cycling is required for the chip to be found (I think I waited 30 minutes of automated reboots once, without seeing a successful boot).

If the USB phy is detected, there seems not to be any problems with the USB communication.

 

The problem seems to be the same as here:

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/zedboard-USB-issue-with-ULPI-timeout/m-p/659226/

but the solution pointed to there does not fix my issue (https://forums.xilinx.com/t5/Embedded-Linux/Petalinux-2015-2-1-usb-not-working/td-p/654349). Perhaps this is because in that thread, the USB was used in host mode, whereas I need peripheral.

 

As suggetsed there, setting the 'usb_phy' in the kernel device tree to

compatible = 'usb-nop-xceive';

does not fix the issue, only hides it.

When using the ulpi-phy driver, at least the kernel deteceted that no ULPI chip was found, and gave an error.

With the usb-nop-xceive, my USB gadget module gets inserted fine, but on half of the boots, nothing happens.

The host side does not detect any USB devices, the Zynq does not get any USB requests.

 

I tried to add a

reset-gpios = <&gpio0 46 1>;

to map the ULPI reset to the kernel (as per Zybo documentation), but it seems this went unused?

Removing that line from the devicetree, and examining GPIO 46 via /sys/class/gpio/ says the GPIO is '1', i.e. reset released both when the device has booted to a working USB setup and when the USB setup has failed.

It could be, ofcourse that something sets this reset pin later, after bootup, and the PHY is in reset when the Chipidea USB tries to configure it. But I am not sure where, when or how to check this.

 

I have tried both with Xilinx's linux tree and with the one Digilent provides for Zybo. Same effect with both. I'd much prefer to work with Xilinx's tree (or even upstream), than Digilent's, as Xilinx's is more up-to-date.

 

The Chipidea IP is set to 'peripheral' mode.

dr_mode = "peripheral"; 

OTG is not required, nor does setting it seem to help the issue.

 

Any ideas on how to fix this, or even where to look for the problem would be greatly appreciated.

 

kalle

 

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3 Replies
Visitor kraiskil
Visitor
10,375 Views
Registered: ‎02-05-2016

Re: Zynq USB phy communication issues

Update:
This doesn't seem to be a Linux issue after all (oops, wrong forum?).
I was able to isolate the same random behaviour to be visible already in u-boot's 'usb start' command.

Zynq> usb start
starting USB...
USB0:   ULPI request timed out 
zynq ULPI viewport init failed
lowlevel init failed
USB1:   usb1 wrong num MIO: 0, Index 1
lowlevel init failed
USB error: all controllers failed lowlevel init

And on the occasional boot it works:

Zynq> usb start
starting USB...
USB0:   USB EHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found
USB1:   usb1 wrong num MIO: 0, Index 1
lowlevel init failed
       scanning usb for storage devices... 0 Storage Device(s) found

Now, if when detection has failed, I manually reset the USB PHY by touching a grounded wire to the PHY chip's RESETN pin (while u-boot waits in its prompt), at the next 'usb start' command the PHY chip is found.

 

Unfortunately, when booting Linux from here on, my own USB kernel module makes the Zynq freeze when inserted.

If the USB PHY is found without the manual reset described above, then my module works just fine.

 

I'm a bit less baffled now, but any thoughts on what is going on would be appreciated.

 

 

kalle

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Teacher muzaffer
Teacher
9,965 Views
Registered: ‎03-31-2012

Re: Zynq USB phy communication issues

This looks like a hardware problem. Do you have a reset generator for the usb PHY? Maybe add an RC circuit to the reset pin so that it's kept low for a while after power is applied that you get a reset to the chip. Another option is to expose the reset pin to the fpga (if not done already) and give it to the driver through emio so that the driver can do the resetting.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Visitor kraiskil
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9,939 Views
Registered: ‎02-05-2016

Re: Zynq USB phy communication issues

After much learning I managed to get the USB available. These are the main points:

 

  1. The configuration file for Vivado describing Zybo's did not route a USB-PHY reset signal to MIO 46, which is where the board has the USB-PHY reset pin routed. I recall getting this configuration from Digilent's page, but perhaps I remember incorrectly.
  2. The pre-compiled u-boot that I used was missing this reset pin aswell.
  3. Reseting the  USB-PHY from u-boot command line (by pulsing the MIO46 with the u-boot gpio commands) did not work. I never checked with an oscilloscope if the reset line was pulsed.
  4. Resetting the USB-PHY from Linux, same effect.

So, finally I got it working by routing the USB reset pin to MIO46 in Vivado, and compiling a new u-boot, using Vivado's generated ps7_init_gpl.c. I edited this file, as it was generated with the reset pin with reverse polarity, but I guess this is just a tick-box in Vivado that I missed.

 

I don't have an explanation on why resetting the USB-PHY later (from u-boot cmd line or linux) would not fix the issue. Perhaps it messed up the Chipidea/Synopsys USB controller IP?

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