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Visitor igor@cellix
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Registered: ‎12-13-2017

Zynq UltraScale+ DisplayPort Live Video Output

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We are interested in using Zynq UltraScale+ DisplayPort Live Video Output for driving LVDS LCD panel through our own PL logic. I don't see any activity in ILA (all zero on dp_video_out_*) except dp_video_ref_clk clock for ILA is there. I guess it's not enabled. I found no PS parameters to enable it. Is there a PS register to do it in s/w?

 

All the Live Video Input signals are grounded. We use ZCU102 with production silicon.

 

I tried to probe AV_BUF_AUD_VID_CLK_SOURCE register, the result was 7 (internal clock is video pipeline clock). I guess it’s OK since we don’t need any Live Video Input.

 

[ re-posted deleted reply to https://forums.xilinx.com/t5/Embedded-Linux/Zynq-UltraScale-Live-Video-Input-Output/td-p/782662 ]

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Moderator
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4,446 Views
Registered: ‎11-09-2015

Re: Zynq UltraScale+ DisplayPort Live Video Output

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Hi igor@cellix,

 

The clock and the timing signals might be separated. It is not because you have the clock that you will have the timing signals on the live output. This is why I was suggesting you to use a VTC on the live input, for test purposes,to see if you have any output on the live output.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Registered: ‎11-09-2015

Re: Zynq UltraScale+ DisplayPort Live Video Output

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Hi igor@cellix,

 

Are you using the Displayport controller output (not live) when using the Live input? If not I am not sure the current driver can support to use only the live output. This might be the reason why you are only seeing the clock on the live output side

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor igor@cellix
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Registered: ‎12-13-2017

Re: Zynq UltraScale+ DisplayPort Live Video Output

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ZCU102 DP port is connected to Dell P2317HWH monitor, LVDS pixel frequency clock (derived from dp_video_ref_clk) is about 65MHz.

fbset output:
mode "1024x768-0"
# D: 0.000 MHz, H: 0.000 kHz, V: 0.000 Hz
geometry 1024 768 1024 1536 16
timings 0 0 0 0 0 0 0
accel true
rgba 5/11,6/5,5/0,0/0
endmode

I noticed that LVDS clock is out of range (no MMCM lock in PL logic) when display is disconnected / shut down on timeout.

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3,257 Views
Registered: ‎11-09-2015

Re: Zynq UltraScale+ DisplayPort Live Video Output

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Hi igor@cellix,

 

So when you are checking the timing signals with the ILA, do you have any outputs on the DELL monitor?

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor igor@cellix
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Registered: ‎12-13-2017

Re: Zynq UltraScale+ DisplayPort Live Video Output

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Yes, the is a picture on the Dell monitor. We have no proper X-window / QT graphics on Linux yet, it's in terminal mode. I suspect dp_video_ref_clk clock is disabled on Dell power-down since ILA hangs when Dell is not online.
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Registered: ‎11-09-2015

Re: Zynq UltraScale+ DisplayPort Live Video Output

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Hi igor@cellix,

 

Yes I would say that the clock is disabled when the Dell monitor power-down. But you are not able to check the ILA when the monitor is up?

 

Again, you need to have the DP live output won't work if the DP output is not working at the same time.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor igor@cellix
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Registered: ‎12-13-2017

Re: Zynq UltraScale+ DisplayPort Live Video Output

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When monitor is up I can "Run trigger immediate" and see the all-zero levels in ILA. No triggering on data enable or horizontal/vertical sync ever happens.

The fact that I need a monitor for Live Video Output clock in Linux is frustrating and defeats the purpose of using LCD instead of DP-connected monitor but I hope to deal with this issue somehow later on - I guess some hacking might be needed.
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Registered: ‎11-09-2015

Re: Zynq UltraScale+ DisplayPort Live Video Output

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Hi igor@cellix,

 

As far as I know, the Xilinx Linux driver currently does not support live output only (not saying that it will never support it). So yes you might need to change the drive if you want to have live output only.

 

However, you should be able see the timing signals when the monitor is connected. I am not 100% familiar with the driver but there should be a switch to change between live timing signals and internal timing signals.

 

If you use a VTC from the PL using the live input, do you see the timing signal on the live output?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor igor@cellix
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Registered: ‎12-13-2017

Re: Zynq UltraScale+ DisplayPort Live Video Output

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Hi Florent,

 

I think I need to explain our hardware set-up, it's is not too complicated.

The following changes were made to "standard" ZCU102 board configuration regarding DP:
In MPSoC PS customization GUI "PS-PL Configuration / General / Others / Live Video" set to 1.

 

The following Block Diagram signals from MPSoC PS are connected to our logic in PL (VTC) and to ILA:
----------------------------
dp_video_out_hsync
dp_video_out_vsync
dp_video_out_pixel1
dp_live_video_de_out
dp_video_ref_clk (ILA clock)
----------------------------

I never saw any activity in ILA on dp_video_out_hsync, dp_video_out_vsync, and dp_live_video_de_out.
Video data on dp_video_out_pixel1 was also always low level.

 

All the MPSoC PS live video inputs tied to GND:
----------------------------
dp_video_in_clk
dp_live_video_in_vsync
dp_live_video_in_hsync
dp_live_video_in_de
dp_live_video_in_pixel1
dp_live_gfx_alpha_in
dp_live_gfx_pixel1_in
dp_external_vsync_event
dp_external_custom_event1
dp_external_custom_event2
----------------------------

 

ILA clock signal dp_video_ref_clk is active when Dell display is up and Linux can output to it.
This clock is also used to clock MMCM in our VTC which is in lock when Dell is up.
I noticed that the clock was active on bare-metal system without any s/w involvement.

 

Our software person is busy with some other tasks at the moment.
I'll get him look at the Linux DP driver ASAP.

 

Best Regards,
Igor

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Registered: ‎11-09-2015

Re: Zynq UltraScale+ DisplayPort Live Video Output

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Hi igor@cellix,

 

The clock and the timing signals might be separated. It is not because you have the clock that you will have the timing signals on the live output. This is why I was suggesting you to use a VTC on the live input, for test purposes,to see if you have any output on the live output.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Visitor igor@cellix
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1,922 Views
Registered: ‎12-13-2017

Re: Zynq UltraScale+ DisplayPort Live Video Output

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Hi Florent, good news, it works!

 

I connected VTC (v_tc) core to Live Video input signals and had Linux output on Live Video outputs / LVDS LCD panel. LCD is 1024x600 native resolution so 1024x768 console output looks a bit cropped at the bottom.

 

The VTC is programmed in default 1024x768p "Generation" mode, "Detection" is disabled, no AXI bus.

 

PS "dp_video_ref_clk" output is connected to PS "dp_video_in_clk" and VTC "clk" inputs.

 

VTC outputs connected to  MPSoC PS Live Video inputs as follows:

 

active_video_out => dp_live_video_in_de

hsync_out => dp_live_video_in_hsync

vsync_out => dp_live_video_in_vsync

 

I guess it's solved. Thanks a lot for your help.

 

In the likely case we'd need your help with the Linux DP driver I'd make a separate post (or our s/w person does).

 

Best Regards,

Igor

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